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author | Yao Yuan <yao.yuan@freescale.com> | 2015-12-05 06:59:13 (GMT) |
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committer | York Sun <yorksun@freescale.com> | 2015-12-15 00:57:32 (GMT) |
commit | 6c4a1eba3fcc013f7d21cdb88098bdd3e7afa75b (patch) | |
tree | 7476f1c1c4ff8f69dd9d410eb4889a784fb3c6ef /arch/arm/cpu/armv7/ls102xa | |
parent | 0b8bc6314e1abc4379cc00f93f949257e0b1b196 (diff) | |
download | u-boot-6c4a1eba3fcc013f7d21cdb88098bdd3e7afa75b.tar.xz |
armv7/fsl-ls102xa: Workaround for DDR erratum A008514
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0042h comes from the hardware team.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/ls102xa')
-rw-r--r-- | arch/arm/cpu/armv7/ls102xa/soc.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 97ba6d5..79ae883 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -76,5 +76,15 @@ int arch_soc_init(void) SCFG_SNPCNFGCR_DBG_RD_WR | SCFG_SNPCNFGCR_EDMA_SNP); + /* + * Memory controller require a register write before being enabled. + * Affects: DDR + * Register: EDDRTQCFG + * Description: Memory controller performance is not optimal with + * default internal target queue register values. + * Workaround: Write a value of 63b2_0042h to address: 157_020Ch. + */ + out_be32(&scfg->eddrtqcfg, 0x63b20042); + return 0; } |