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| author | Xiaoliang Yang <xiaoliang.yang@nxp.com> | 2016-09-14 03:36:14 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-10-06 16:55:08 (GMT) |
| commit | f85a8e8d1db374d894afc03504a0eead1de99f74 (patch) | |
| tree | 19af1b973cc4b09f23a15cd26400bcf7fb88845c /arch/arm/cpu/armv7/ls102xa | |
| parent | b259732d36ccdc911e5b3ed83bd55aae90a43532 (diff) | |
| download | u-boot-f85a8e8d1db374d894afc03504a0eead1de99f74.tar.xz | |
armv7: LS1021a: enable i-cache in start.S
Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.
Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv7/ls102xa')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/soc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 31f00cb..52fb6f8 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -60,6 +60,10 @@ unsigned int get_soc_major_rev(void) return major; } +void s_init(void) +{ +} + #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 void erratum_a010315(void) { |