diff options
author | Tom Rini <trini@konsulko.com> | 2015-08-02 11:40:37 (GMT) |
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committer | Tom Rini <trini@konsulko.com> | 2015-08-02 11:40:37 (GMT) |
commit | 7a1af7a79bd79ded6a78d0c1afdbc3353669e313 (patch) | |
tree | 6adcb6dfb2782e8502ca07e2533bee3f95eaeae9 /arch/arm/cpu/armv7/mx6/soc.c | |
parent | 8968b914be7bfd67d179d0395898bd9db67aaad1 (diff) | |
parent | f85764cc1f6ab01ffc60dd78de9c4de4cff2b5ce (diff) | |
download | u-boot-7a1af7a79bd79ded6a78d0c1afdbc3353669e313.tar.xz |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/soc.c')
-rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 29de624..8ad8da8 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -62,12 +62,12 @@ u32 get_cpu_rev(void) struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 reg = readl(&anatop->digprog_sololite); u32 type = ((reg >> 16) & 0xff); - u32 major; + u32 major, cfg = 0; if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; - u32 cfg = readl(&scu->config) & 3; + cfg = readl(&scu->config) & 3; type = ((reg >> 16) & 0xff); if (type == MXC_CPU_MX6DL) { if (!cfg) @@ -81,6 +81,13 @@ u32 get_cpu_rev(void) } major = ((reg >> 8) & 0xff); + if ((major >= 1) && + ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) { + major--; + type = MXC_CPU_MX6QP; + if (cfg == 1) + type = MXC_CPU_MX6DP; + } reg &= 0xff; /* mx6 silicon revision */ return (type << 12) | (reg + (0x10 * (major + 1))); } @@ -309,11 +316,10 @@ static void imx_set_wdog_powerdown(bool enable) { struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; - -#ifdef CONFIG_MX6SX struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; - writew(enable, &wdog3->wmcr); -#endif + + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) + writew(enable, &wdog3->wmcr); /* Write to the PDE (Power Down Enable) bit */ writew(enable, &wdog1->wmcr); @@ -335,9 +341,12 @@ static void set_ahb_rate(u32 val) static void clear_mmdc_ch_mask(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - writel(0, &mxc_ccm->ccdr); + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); + writel(reg, &mxc_ccm->ccdr); } static void init_bandgap(void) @@ -520,7 +529,7 @@ void s_init(void) u32 mask528; u32 reg, periph1, periph2; - if (is_cpu_type(MXC_CPU_MX6SX)) + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) return; /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs |