diff options
author | Eric Nelson <eric@nelint.com> | 2016-10-30 23:33:50 (GMT) |
---|---|---|
committer | Stefano Babic <sbabic@denx.de> | 2016-11-29 15:40:37 (GMT) |
commit | a425bf72816abbc3996540e42c33a386e8b8a221 (patch) | |
tree | acdb411f74583f4764ece3332903e3c337f68511 /arch/arm/cpu/armv7/mx6 | |
parent | 48c7d4379bcf70ce331e441b135cfbf3546dd574 (diff) | |
download | u-boot-a425bf72816abbc3996540e42c33a386e8b8a221.tar.xz |
ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines
The DDR calibration routines are gated by conditionals for the
i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.
Also, since only the Novena board currently uses the dynamic
DDR calibration routines, these routines waste space on other
boards using SPL.
Add a KConfig entry to allow boards to selectively include the
DDR calibration routines.
Signed-off-by: Eric Nelson <eric@nelint.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6')
-rw-r--r-- | arch/arm/cpu/armv7/mx6/Kconfig | 8 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/mx6/ddr.c | 3 |
2 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 762a581..8b2217e 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -35,6 +35,14 @@ config MX6ULL bool select MX6UL +config MX6_DDRCAL + bool "Include dynamic DDR calibration routines" + depends on SPL + default n + help + Say "Y" if your board uses dynamic (per-boot) DDR calibration. + If unsure, say N. + choice prompt "MX6 board select" optional diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index b12fb64..0cf391e 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -14,8 +14,7 @@ #include <asm/types.h> #include <wait_bit.h> -#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) - +#if defined(CONFIG_MX6_DDRCAL) static void reset_read_data_fifos(void) { struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; |