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author | Lokesh Vutla <lokeshvutla@ti.com> | 2012-05-22 00:03:24 (GMT) |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-07-07 12:07:23 (GMT) |
commit | 43037d76316db1a53be16a4c1ed97203257fa4ee (patch) | |
tree | c549887069235d35144830a8ec0bcf9346c1d1ca /arch/arm/cpu/armv7/omap4 | |
parent | eb4e18e89eec8d63f064cb5ec597ba9387fe4987 (diff) | |
download | u-boot-43037d76316db1a53be16a4c1ed97203257fa4ee.tar.xz |
OMAP5: ADD precalculated timings for ddr3
Adding precalculated timings for ddr3 with 1cs
adding required registers for ddr3
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap4')
-rw-r--r-- | arch/arm/cpu/armv7/omap4/sdram_elpida.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index b538960..239ad2b 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -92,6 +92,7 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { /* Dummy registers for OMAP44xx */ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, |