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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-11 20:24:28 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-11 20:24:28 (GMT) |
| commit | cac423a730d3506154744485af1bbc1cd3a1e6a8 (patch) | |
| tree | 358b627972d9125de573c623f33e2da789f1de51 /arch/arm/cpu/armv7/omap5/hw_data.c | |
| parent | c1b43ac7699640c8086bd73faa798bc9722d32c9 (diff) | |
| parent | 47c6ea076eb51e624f8744d93db5cd70b97dc25d (diff) | |
| download | u-boot-cac423a730d3506154744485af1bbc1cd3a1e6a8.tar.xz | |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ced274e..604fa42 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -41,7 +41,7 @@ struct dplls const **dplls_data = struct vcores_data const **omap_vcores = (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; struct omap_sys_ctrl_regs const **ctrl = - (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL; + (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; /* OPP HIGH FREQUENCY for ES2.0 */ static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { @@ -403,6 +403,7 @@ void enable_basic_uboot_clocks(void) }; u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -411,7 +412,7 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l4per_i2c2_clkctrl, (*prcm)->cm_l4per_i2c3_clkctrl, (*prcm)->cm_l4per_i2c4_clkctrl, - (*prcm)->cm_l3init_hsusbtll_clkctrl, + (*prcm)->cm_l4per_i2c5_clkctrl, (*prcm)->cm_l3init_hsusbhost_clkctrl, (*prcm)->cm_l3init_fsusb_clkctrl, 0 |