diff options
| author | SRICHARAN R <r.sricharan@ti.com> | 2013-11-08 12:10:37 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-04 13:12:08 (GMT) |
| commit | 6c70935d7525a4b2b144b49457d2bae85f1d111a (patch) | |
| tree | 663b91f30c048968bcef5a4bf3916b123c51f7ab /arch/arm/cpu/armv7/omap5/hwinit.c | |
| parent | 39302dcd3013134e936cc76ccee8d1ed5522bfa0 (diff) | |
| download | u-boot-6c70935d7525a4b2b144b49457d2bae85f1d111a.tar.xz | |
ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hwinit.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hwinit.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 1065891..82c8638 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -297,13 +297,17 @@ void srcomp_enable(void) void config_data_eye_leveling_samples(u32 emif_base) { + const struct ctrl_ioregs *ioregs; + + get_ioregs(&ioregs); + /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ if (emif_base == EMIF1_BASE) - writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - (*ctrl)->control_emif1_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext_final, + (*ctrl)->control_emif1_sdram_config_ext); else if (emif_base == EMIF2_BASE) - writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - (*ctrl)->control_emif2_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext_final, + (*ctrl)->control_emif2_sdram_config_ext); } void init_omap_revision(void) |