arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platforms

This moves what was in arch/arm/cpu/armv7/omap-common in to
arch/arm/mach-omap2 and moves
arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
as subdirectories.  All refernces to the former locations are updated to
the current locations.  For the logic to decide what our outputs are,
consolidate the tests into a single config.mk rather than including 4.

Signed-off-by: Tom Rini <trini@konsulko.com>

13 files changed, 0 insertions, 3963 deletions

diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig
deleted file mode 100644
index 22259dc..0000000
--- a/arch/arm/cpu/armv7/omap5/Kconfig
+++ /dev/null
@@ -1,94 +0,0 @@
-if OMAP54XX
-
-config SPL_EXT_SUPPORT
-	default y
-
-config SPL_FAT_SUPPORT
-	default y
-
-config SPL_GPIO_SUPPORT
-	default y
-
-config SPL_I2C_SUPPORT
-	default y
-
-config SPL_LIBCOMMON_SUPPORT
-	default y
-
-config SPL_LIBDISK_SUPPORT
-	default y
-
-config SPL_LIBGENERIC_SUPPORT
-	default y
-
-config SPL_MMC_SUPPORT
-	default y
-
-config SPL_NAND_SUPPORT
-	default y
-
-config SPL_POWER_SUPPORT
-	default y
-
-config SPL_SERIAL_SUPPORT
-	default y
-
-config SPL_DISPLAY_PRINT
-	default y
-
-choice
-	prompt "OMAP5 board select"
-	optional
-
-config TARGET_CM_T54
-	bool "CompuLab CM-T54"
-
-config TARGET_OMAP5_UEVM
-	bool "TI OMAP5 uEVM board"
-
-config TARGET_DRA7XX_EVM
-	bool "TI DRA7XX"
-	select TI_I2C_BOARD_DETECT
-	select PHYS_64BIT
-
-config TARGET_AM57XX_EVM
-	bool "AM57XX"
-	select TI_I2C_BOARD_DETECT
-
-endchoice
-
-config SYS_SOC
-	default "omap5"
-
-config TI_SECURE_EMIF_REGION_START
-	hex "Reserved EMIF region start address"
-	depends on TI_SECURE_DEVICE
-	default 0x0
-	help
-	  Reserved EMIF region start address. Set to "0" to auto-select
-	  to be at the end of the external memory region.
-
-config TI_SECURE_EMIF_TOTAL_REGION_SIZE
-	hex "Reserved EMIF region size"
-	depends on TI_SECURE_DEVICE
-	default 0x0
-	help
-	  Total reserved EMIF region size. Default is 0, which means no reserved EMIF
-	  region on secure devices.
-
-config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
-	hex "Size of protected region within reserved EMIF region"
-	depends on TI_SECURE_DEVICE
-	default 0x0
-	help
-	  This config option is used to specify the size of the portion of the total
-	  reserved EMIF region set aside for secure OS needs that will  be protected
-	  using hardware memory firewalls. This value must be smaller than the
-	  TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
-
-source "board/compulab/cm_t54/Kconfig"
-source "board/ti/omap5_uevm/Kconfig"
-source "board/ti/dra7xx/Kconfig"
-source "board/ti/am57xx/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
deleted file mode 100644
index 0212df7..0000000
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2000-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= boot.o
-obj-y	+= hwinit.o
-obj-y	+= emif.o
-obj-y	+= sdram.o
-obj-y	+= prcm-regs.o
-obj-y	+= hw_data.o
-obj-y	+= abb.o
-obj-y	+= fdt.o
-obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
-obj-$(CONFIG_TI_SECURE_DEVICE) += sec-fxns.o
diff --git a/arch/arm/cpu/armv7/omap5/abb.c b/arch/arm/cpu/armv7/omap5/abb.c
deleted file mode 100644
index 3bf8897..0000000
--- a/arch/arm/cpu/armv7/omap5/abb.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Adaptive Body Bias programming sequence for OMAP5 family
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/omap_common.h>
-#include <asm/io.h>
-
-/*
- * Setup LDOVBB for OMAP5.
- * On OMAP5+ some ABB settings are fused. They are handled
- * in the following way:
- *
- * 1. corresponding EFUSE register contains ABB enable bit
- *    and VSET value
- * 2. If ABB enable bit is set to 1, than ABB should be
- *    enabled, otherwise ABB should be disabled
- * 3. If ABB is enabled, than VSET value should be copied
- *    to corresponding MUX control register
- */
-s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
-{
-	u32 vset;
-	u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
-	u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
-
-	if (!is_omap54xx()) {
-		/* DRA7 */
-		fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
-		fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
-	}
-	/*
-	 * ABB parameters must be properly fused
-	 * otherwise ABB should be disabled
-	 */
-	vset = readl(fuse);
-	if (!(vset & fuse_enable_mask))
-		return -1;
-
-	/* prepare VSET value for LDOVBB mux register */
-	vset &= fuse_vset_mask;
-	vset >>= ffs(fuse_vset_mask) - 1;
-	vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
-	vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;
-
-	/* setup LDOVBB using fused value */
-	clrsetbits_le32(ldovbb,  OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK, vset);
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/omap5/boot.c b/arch/arm/cpu/armv7/omap5/boot.c
deleted file mode 100644
index 583becc..0000000
--- a/arch/arm/cpu/armv7/omap5/boot.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * OMAP5 boot
- *
- * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/omap_common.h>
-#include <spl.h>
-
-static u32 boot_devices[] = {
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-	BOOT_DEVICE_MMC2,
-	BOOT_DEVICE_NAND,
-	BOOT_DEVICE_MMC1,
-	BOOT_DEVICE_SATA,
-	BOOT_DEVICE_XIP,
-	BOOT_DEVICE_XIP,
-	BOOT_DEVICE_SPI,
-	BOOT_DEVICE_SPI,
-#else
-	BOOT_DEVICE_MMC2,
-	BOOT_DEVICE_NAND,
-	BOOT_DEVICE_MMC1,
-	BOOT_DEVICE_SATA,
-	BOOT_DEVICE_XIP,
-	BOOT_DEVICE_MMC2,
-	BOOT_DEVICE_XIPWAIT,
-#endif
-};
-
-u32 omap_sys_boot_device(void)
-{
-	u32 sys_boot;
-
-	/* Grab the first 4 bits of the status register for SYS_BOOT. */
-	sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 4) - 1);
-
-	if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
-		return BOOT_DEVICE_NONE;
-
-	return boot_devices[sys_boot];
-}
diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
deleted file mode 100644
index 286ca86..0000000
--- a/arch/arm/cpu/armv7/omap5/config.mk
+++ /dev/null
@@ -1,22 +0,0 @@
-#
-# Copyright 2011 Linaro Limited
-#
-# Aneesh V <annesh@ti.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include  $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
-
-ifdef CONFIG_SPL_BUILD
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-ALL-y	+= u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER
-else
-ALL-y	+= MLO
-endif
-else
-ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
-ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img
-endif
-ALL-y	+= u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c b/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c
deleted file mode 100644
index 8798730..0000000
--- a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * (C) Copyright 2015
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Lokesh Vutla <lokeshvutla@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/utils.h>
-#include <asm/arch/dra7xx_iodelay.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux_dra7xx.h>
-#include <asm/omap_common.h>
-
-static int isolate_io(u32 isolate)
-{
-	if (isolate) {
-		clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ,
-				SDCARD_PWRDNZ);
-		clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ,
-				SDCARD_BIAS_PWRDNZ);
-	}
-
-	/* Override control on ISOCLKIN signal to IO pad ring. */
-	clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
-			PMCTRL_ISOCLK_OVERRIDE_CTRL);
-	if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK,
-			   (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
-		return ERR_DEISOLATE_IO << isolate;
-
-	/* Isolate/Deisolate IO */
-	clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK,
-			isolate << CTRL_ISOLATE_SHIFT);
-	/* Dummy read to add delay t > 10ns */
-	readl((*ctrl)->ctrl_core_sma_sw_0);
-
-	/* Return control on ISOCLKIN to hardware */
-	clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK,
-			PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL);
-	if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK,
-			   0 << PMCTRL_ISOCLK_STATUS_SHIFT,
-			   (u32 *)(*prcm)->prm_io_pmctrl, LDELAY))
-		return ERR_DEISOLATE_IO << isolate;
-
-	return 0;
-}
-
-static int calibrate_iodelay(u32 base)
-{
-	u32 reg;
-
-	/* Configure REFCLK period */
-	reg = readl(base + CFG_REG_2_OFFSET);
-	reg &= ~CFG_REG_REFCLK_PERIOD_MASK;
-	reg |= CFG_REG_REFCLK_PERIOD;
-	writel(reg, base + CFG_REG_2_OFFSET);
-
-	/* Initiate Calibration */
-	clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK,
-			CFG_REG_CALIB_STRT << CFG_REG_CALIB_STRT_SHIFT);
-	if (!wait_on_value(CFG_REG_CALIB_STRT_MASK, CFG_REG_CALIB_END,
-			   (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
-		return ERR_CALIBRATE_IODELAY;
-
-	return 0;
-}
-
-static int update_delay_mechanism(u32 base)
-{
-	/* Initiate the reload of calibrated values. */
-	clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK,
-			CFG_REG_ROM_READ_START);
-	if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END,
-			   (u32 *)(base + CFG_REG_0_OFFSET), LDELAY))
-		return ERR_UPDATE_DELAY;
-
-	return 0;
-}
-
-static u32 calculate_delay(u32 base, u16 offset, u16 den)
-{
-	u16 refclk_period, dly_cnt, ref_cnt;
-	u32 reg, q, r;
-
-	refclk_period = readl(base + CFG_REG_2_OFFSET) &
-			      CFG_REG_REFCLK_PERIOD_MASK;
-
-	reg = readl(base + offset);
-	dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT;
-	ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT;
-
-	if (!dly_cnt || !den)
-		return 0;
-
-	/*
-	 * To avoid overflow and integer truncation, delay value
-	 * is calculated as quotient + remainder.
-	 */
-	q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den));
-	r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) /
-		(2 * dly_cnt * den);
-
-	return q + r;
-}
-
-static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde)
-{
-	u32 g_delay_coarse, g_delay_fine;
-	u32 a_delay_coarse, a_delay_fine;
-	u32 c_elements, f_elements;
-	u32 total_delay, reg = 0;
-
-	g_delay_coarse = g_delay / 920;
-	g_delay_fine = ((g_delay % 920) * 10) / 60;
-
-	a_delay_coarse = a_delay / cpde;
-	a_delay_fine = ((a_delay % cpde) * 10) / fpde;
-
-	c_elements = g_delay_coarse + a_delay_coarse;
-	f_elements = (g_delay_fine + a_delay_fine) / 10;
-
-	if (f_elements > 22) {
-		total_delay = c_elements * cpde + f_elements * fpde;
-
-		c_elements = total_delay / cpde;
-		f_elements = (total_delay % cpde) / fpde;
-	}
-
-	reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK;
-	reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK;
-	reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT;
-	reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT;
-
-	return reg;
-}
-
-int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
-		   int niodelays)
-{
-	struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
-	u32 reg, cpde, fpde, i;
-
-	if (!niodelays)
-		return 0;
-
-	cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET,
-			       88);
-	if (!cpde)
-		return ERR_CPDE;
-
-	fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET,
-			       264);
-	if (!fpde)
-		return ERR_FPDE;
-
-	for (i = 0; i < niodelays; i++, iodelay++) {
-		reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde,
-				  fpde);
-		writel(reg, base + iodelay->offset);
-	}
-
-	return 0;
-}
-
-int __recalibrate_iodelay_start(void)
-{
-	int ret = 0;
-
-	/* IO recalibration should be done only from SRAM */
-	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
-		puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
-		return -1;
-	}
-
-	/* unlock IODELAY CONFIG registers */
-	writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base +
-	       CFG_REG_8_OFFSET);
-
-	ret = calibrate_iodelay((*ctrl)->iodelay_config_base);
-	if (ret)
-		goto err;
-
-	ret = isolate_io(ISOLATE_IO);
-	if (ret)
-		goto err;
-
-	ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
-
-err:
-	return ret;
-}
-
-void __recalibrate_iodelay_end(int ret)
-{
-
-	/* IO recalibration should be done only from SRAM */
-	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
-		puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
-		return;
-	}
-
-	if (!ret)
-		ret = isolate_io(DEISOLATE_IO);
-
-	/* lock IODELAY CONFIG registers */
-	writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
-	       CFG_REG_8_OFFSET);
-
-	/*
-	 * UART cannot be used during IO recalibration sequence as IOs are in
-	 * isolation. So error handling and debug prints are done after
-	 * complete IO delay recalibration sequence
-	 */
-	switch (ret) {
-	case ERR_CALIBRATE_IODELAY:
-		puts("IODELAY: IO delay calibration sequence failed\n");
-		break;
-	case ERR_ISOLATE_IO:
-		puts("IODELAY: Isolation of Device IOs failed\n");
-		break;
-	case ERR_UPDATE_DELAY:
-		puts("IODELAY: Delay mechanism update with new calibrated values failed\n");
-		break;
-	case ERR_DEISOLATE_IO:
-		puts("IODELAY: De-isolation of Device IOs failed\n");
-		break;
-	case ERR_CPDE:
-		puts("IODELAY: CPDE calculation failed\n");
-		break;
-	case ERR_FPDE:
-		puts("IODELAY: FPDE calculation failed\n");
-		break;
-	case -1:
-		puts("IODELAY: Wrong Context call?\n");
-		break;
-	default:
-		debug("IODELAY: IO delay recalibration successfully completed\n");
-	}
-
-	return;
-}
-
-void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
-			   struct iodelay_cfg_entry const *iodelay,
-			   int niodelays)
-{
-	int ret = 0;
-
-	/* IO recalibration should be done only from SRAM */
-	if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
-		puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
-		return;
-	}
-
-	ret = __recalibrate_iodelay_start();
-	if (ret)
-		goto err;
-
-	/* Configure Mux settings */
-	do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
-
-	/* Configure Manual IO timing modes */
-	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
-	if (ret)
-		goto err;
-
-err:
-	__recalibrate_iodelay_end(ret);
-
-}
diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c
deleted file mode 100644
index b1203a3..0000000
--- a/arch/arm/cpu/armv7/omap5/emif.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * EMIF programming
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com> for OMAP4
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/emif.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
-static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
-static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
-#endif
-
-#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-/* Base AC Timing values specified by JESD209-2 for 532MHz operation */
-static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
-	.max_freq = 532000000,
-	.RL = 8,
-	.tRPab = 21,
-	.tRCD = 18,
-	.tWR = 15,
-	.tRASmin = 42,
-	.tRRD = 10,
-	.tWTRx2 = 15,
-	.tXSR = 140,
-	.tXPx2 = 15,
-	.tRFCab = 130,
-	.tRTPx2 = 15,
-	.tCKE = 3,
-	.tCKESR = 15,
-	.tZQCS = 90,
-	.tZQCL = 360,
-	.tZQINIT = 1000,
-	.tDQSCKMAXx2 = 11,
-	.tRASmax = 70,
-	.tFAW = 50
-};
-
-/*
- * Min tCK values specified by JESD209-2
- * Min tCK specifies the minimum duration of some AC timing parameters in terms
- * of the number of cycles. If the calculated number of cycles based on the
- * absolute time value is less than the min tCK value, min tCK value should
- * be used instead. This typically happens at low frequencies.
- */
-static const struct lpddr2_min_tck min_tck_jedec = {
-	.tRL = 3,
-	.tRP_AB = 3,
-	.tRCD = 3,
-	.tWR = 3,
-	.tRAS_MIN = 3,
-	.tRRD = 2,
-	.tWTR = 2,
-	.tXP = 2,
-	.tRTP = 2,
-	.tCKE = 3,
-	.tCKESR = 3,
-	.tFAW = 8
-};
-
-static const struct lpddr2_ac_timings const*
-			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
-	&timings_jedec_532_mhz
-};
-
-static const struct lpddr2_device_timings jedec_default_timings = {
-	.ac_timings = jedec_ac_timings,
-	.min_tck = &min_tck_jedec
-};
-
-void emif_get_device_timings(u32 emif_nr,
-		const struct lpddr2_device_timings **cs0_device_timings,
-		const struct lpddr2_device_timings **cs1_device_timings)
-{
-	/* Assume Identical devices on EMIF1 & EMIF2 */
-	*cs0_device_timings = &jedec_default_timings;
-	*cs1_device_timings = NULL;
-}
-#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/cpu/armv7/omap5/fdt.c b/arch/arm/cpu/armv7/omap5/fdt.c
deleted file mode 100644
index da8d59b..0000000
--- a/arch/arm/cpu/armv7/omap5/fdt.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * Copyright 2016 Texas Instruments, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <malloc.h>
-
-#include <asm/omap_common.h>
-#include <asm/arch-omap5/sys_proto.h>
-
-#ifdef CONFIG_TI_SECURE_DEVICE
-
-/* Give zero values if not already defined */
-#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
-#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
-#endif
-#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
-#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
-#endif
-
-static u32 hs_irq_skip[] = {
-	8,	/* Secure violation reporting interrupt */
-	15,	/* One interrupt for SDMA by secure world */
-	118	/* One interrupt for Crypto DMA by secure world */
-};
-
-static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
-{
-	const char *path;
-	int offs;
-	int ret;
-	int len, i, old_cnt, new_cnt;
-	u32 *temp;
-	const u32 *p_data;
-
-	/*
-	 * Increase the size of the fdt
-	 * so we have some breathing room
-	 */
-	ret = fdt_increase_size(fdt, 512);
-	if (ret < 0) {
-		printf("Could not increase size of device tree: %s\n",
-		       fdt_strerror(ret));
-		return ret;
-	}
-
-	/* Reserve IRQs that are used/needed by secure world */
-	path = "/ocp/crossbar";
-	offs = fdt_path_offset(fdt, path);
-	if (offs < 0) {
-		debug("Node %s not found.\n", path);
-		return 0;
-	}
-
-	/* Get current entries */
-	p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
-	if (p_data)
-		old_cnt = len / sizeof(u32);
-	else
-		old_cnt = 0;
-
-	new_cnt = sizeof(hs_irq_skip) /
-				sizeof(hs_irq_skip[0]);
-
-	/* Create new/updated skip list for HS parts */
-	temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
-	for (i = 0; i < new_cnt; i++)
-		temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
-	for (i = 0; i < old_cnt; i++)
-		temp[i + new_cnt] = p_data[i];
-
-	/* Blow away old data and set new data */
-	fdt_delprop(fdt, offs, "ti,irqs-skip");
-	ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
-			  temp,
-			  (old_cnt + new_cnt) * sizeof(u32));
-	free(temp);
-
-	/* Check if the update worked */
-	if (ret < 0) {
-		printf("Could not add ti,irqs-skip property to node %s: %s\n",
-		       path, fdt_strerror(ret));
-		return ret;
-	}
-
-	return 0;
-}
-
-static int ft_hs_disable_rng(void *fdt, bd_t *bd)
-{
-	const char *path;
-	int offs;
-	int ret;
-
-	/* Make HW RNG reserved for secure world use */
-	path = "/ocp/rng";
-	offs = fdt_path_offset(fdt, path);
-	if (offs < 0) {
-		debug("Node %s not found.\n", path);
-		return 0;
-	}
-	ret = fdt_setprop_string(fdt, offs,
-				 "status", "disabled");
-	if (ret < 0) {
-		printf("Could not add status property to node %s: %s\n",
-		       path, fdt_strerror(ret));
-		return ret;
-	}
-	return 0;
-}
-
-#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
-    (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
-static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
-{
-	const char *path;
-	int offs;
-	int ret;
-	u32 temp[2];
-
-	/*
-	 * Update SRAM reservations on secure devices. The OCMC RAM
-	 * is always reserved for secure use from the start of that
-	 * memory region
-	 */
-	path = "/ocp/ocmcram@40300000/sram-hs";
-	offs = fdt_path_offset(fdt, path);
-	if (offs < 0) {
-		debug("Node %s not found.\n", path);
-		return 0;
-	}
-
-	/* relative start offset */
-	temp[0] = cpu_to_fdt32(0);
-	/* reservation size */
-	temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
-				   CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
-	fdt_delprop(fdt, offs, "reg");
-	ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
-	if (ret < 0) {
-		printf("Could not add reg property to node %s: %s\n",
-		       path, fdt_strerror(ret));
-		return ret;
-	}
-
-	return 0;
-}
-#else
-static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
-#endif
-
-#if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE != 0)
-static int ft_hs_fixup_dram(void *fdt, bd_t *bd)
-{
-	const char *path, *subpath;
-	int offs;
-	u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
-	u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
-	fdt64_t temp[2];
-
-	/* If start address is zero, place at end of DRAM */
-	if (0 == sec_mem_start)
-		sec_mem_start =
-			(CONFIG_SYS_SDRAM_BASE +
-			(omap_sdram_size() - sec_mem_size));
-
-	/* Delete any original secure_reserved node */
-	path = "/reserved-memory/secure_reserved";
-	offs = fdt_path_offset(fdt, path);
-	if (offs >= 0)
-		fdt_del_node(fdt, offs);
-
-	/* Add new secure_reserved node */
-	path = "/reserved-memory";
-	offs = fdt_path_offset(fdt, path);
-	if (offs < 0) {
-		debug("Node %s not found\n", path);
-		path = "/";
-		subpath = "reserved-memory";
-		fdt_path_offset(fdt, path);
-		offs = fdt_add_subnode(fdt, offs, subpath);
-		if (offs < 0) {
-			printf("Could not create %s%s node.\n", path, subpath);
-			return 1;
-		}
-		path = "/reserved-memory";
-		offs = fdt_path_offset(fdt, path);
-	}
-
-	subpath = "secure_reserved";
-	offs = fdt_add_subnode(fdt, offs, subpath);
-	if (offs < 0) {
-		printf("Could not create %s%s node.\n", path, subpath);
-		return 1;
-	}
-
-	temp[0] = cpu_to_fdt64(((u64)sec_mem_start));
-	temp[1] = cpu_to_fdt64(((u64)sec_mem_size));
-	fdt_setprop_string(fdt, offs, "compatible",
-			   "ti,dra7-secure-memory");
-	fdt_setprop_string(fdt, offs, "status", "okay");
-	fdt_setprop(fdt, offs, "no-map", NULL, 0);
-	fdt_setprop(fdt, offs, "reg", temp, sizeof(temp));
-
-	return 0;
-}
-#else
-static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; }
-#endif
-
-static void ft_hs_fixups(void *fdt, bd_t *bd)
-{
-	/* Check we are running on an HS/EMU device type */
-	if (GP_DEVICE != get_device_type()) {
-		if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
-		    (ft_hs_disable_rng(fdt, bd) == 0) &&
-		    (ft_hs_fixup_sram(fdt, bd) == 0) &&
-		    (ft_hs_fixup_dram(fdt, bd) == 0))
-			return;
-	} else {
-		printf("ERROR: Incorrect device type (GP) detected!");
-	}
-	/* Fixup failed or wrong device type */
-	hang();
-}
-#else
-static void ft_hs_fixups(void *fdt, bd_t *bd)
-{
-}
-#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
-
-/*
- * Place for general cpu/SoC FDT fixups. Board specific
- * fixups should remain in the board files which is where
- * this function should be called from.
- */
-void ft_cpu_setup(void *fdt, bd_t *bd)
-{
-	ft_hs_fixups(fdt, bd);
-}
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
deleted file mode 100644
index fc99135..0000000
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/*
- *
- * HW data initialization for OMAP5
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <palmas.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/arch/clock.h>
-#include <asm/omap_gpio.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-
-struct prcm_regs const **prcm =
-			(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
-struct dplls const **dplls_data =
-			(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
-struct vcores_data const **omap_vcores =
-		(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
-struct omap_sys_ctrl_regs const **ctrl =
-	(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
-
-/* OPP HIGH FREQUENCY for ES2.0 */
-static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
-	{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
-};
-
-/* OPP NOM FREQUENCY for ES1.0 */
-static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
-	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
-};
-
-/* OPP LOW FREQUENCY for ES1.0 */
-static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
-	{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
-};
-
-/* OPP LOW FREQUENCY for ES2.0 */
-static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
-	{499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
-};
-
-/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
-static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
-	{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
-	{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
-	{119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
-	{625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
-};
-
-static const struct dpll_params
-			core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
-	{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 16.8 MHz */
-	{277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 19.2 MHz */
-	{368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}		/* 38.4 MHz */
-};
-
-static const struct dpll_params
-			core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
-	{266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 16.8 MHz */
-	{277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 19.2 MHz */
-	{368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}		/* 38.4 MHz */
-};
-
-static const struct dpll_params
-		core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
-	{266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 12 MHz   */
-	{266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 20 MHz   */
-	{443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 16.8 MHz */
-	{277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 19.2 MHz */
-	{368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 38.4 MHz */
-};
-
-static const struct dpll_params
-			core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
-	{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 16.8 MHz */
-	{277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 19.2 MHz */
-	{368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}		/* 38.4 MHz */
-};
-
-static const struct dpll_params
-			core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
-	{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 16.8 MHz */
-	{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 19.2 MHz */
-	{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}		/* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
-	{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 16.8 MHz */
-	{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 19.2 MHz */
-	{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}		/* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
-	{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 16.8 MHz */
-	{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 19.2 MHz */
-	{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}		/* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
-	{32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 12 MHz   */
-	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
-	{160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 16.8 MHz */
-	{20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 19.2 MHz */
-	{192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
-	{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
-	{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
-	{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
-	{1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz */
-	{208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
-	{182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
-	{224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
-		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
-	{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
-	{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
-	{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
-	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
-};
-
-/* ABE M & N values with sysclk2(22.5792 MHz) as input */
-static const struct dpll_params
-		abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
-};
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
-	{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
-	{480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 20 MHz   */
-	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
-};
-
-static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
-	{111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
-	{333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
-	{555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
-	{555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
-	{666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
-};
-
-static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
-	{266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
-	{266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
-	{190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
-	{665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
-	{532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
-};
-
-static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
-	{250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 12 MHz   */
-	{250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 20 MHz   */
-	{119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 16.8 MHz */
-	{625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 38.4 MHz */
-};
-
-struct dplls omap5_dplls_es1 = {
-	.mpu = mpu_dpll_params_800mhz,
-	.core = core_dpll_params_2128mhz_ddr532,
-	.per = per_dpll_params_768mhz,
-	.iva = iva_dpll_params_2330mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
-	.abe = abe_dpll_params_sysclk_196608khz,
-#else
-	.abe = &abe_dpll_params_32k_196608khz,
-#endif
-	.usb = usb_dpll_params_1920mhz,
-	.ddr = NULL
-};
-
-struct dplls omap5_dplls_es2 = {
-	.mpu = mpu_dpll_params_1ghz,
-	.core = core_dpll_params_2128mhz_ddr532_es2,
-	.per = per_dpll_params_768mhz_es2,
-	.iva = iva_dpll_params_2330mhz,
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
-	.abe = abe_dpll_params_sysclk_196608khz,
-#else
-	.abe = &abe_dpll_params_32k_196608khz,
-#endif
-	.usb = usb_dpll_params_1920mhz,
-	.ddr = NULL
-};
-
-struct dplls dra7xx_dplls = {
-	.mpu = mpu_dpll_params_1ghz,
-	.core = core_dpll_params_2128mhz_dra7xx,
-	.per = per_dpll_params_768mhz_dra7xx,
-	.abe = abe_dpll_params_sysclk2_361267khz,
-	.iva = iva_dpll_params_2330mhz_dra7xx,
-	.usb = usb_dpll_params_1920mhz,
-	.ddr = ddr_dpll_params_2128mhz,
-	.gmac = gmac_dpll_params_2000mhz,
-};
-
-struct dplls dra72x_dplls = {
-	.mpu = mpu_dpll_params_1ghz,
-	.core = core_dpll_params_2128mhz_dra7xx,
-	.per = per_dpll_params_768mhz_dra7xx,
-	.abe = abe_dpll_params_sysclk2_361267khz,
-	.iva = iva_dpll_params_2330mhz_dra7xx,
-	.usb = usb_dpll_params_1920mhz,
-	.ddr =	ddr_dpll_params_2664mhz,
-	.gmac = gmac_dpll_params_2000mhz,
-};
-
-struct pmic_data palmas = {
-	.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
-	.step = 10000, /* 10 mV represented in uV */
-	/*
-	 * Offset codes 1-6 all give the base voltage in Palmas
-	 * Offset code 0 switches OFF the SMPS
-	 */
-	.start_code = 6,
-	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
-	.pmic_bus_init	= sri2c_init,
-	.pmic_write	= omap_vc_bypass_send_value,
-	.gpio_en = 0,
-};
-
-/* The TPS659038 and TPS65917 are software-compatible, use common struct */
-struct pmic_data tps659038 = {
-	.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
-	.step = 10000, /* 10 mV represented in uV */
-	/*
-	 * Offset codes 1-6 all give the base voltage in Palmas
-	 * Offset code 0 switches OFF the SMPS
-	 */
-	.start_code = 6,
-	.i2c_slave_addr	= TPS659038_I2C_SLAVE_ADDR,
-	.pmic_bus_init	= gpi2c_init,
-	.pmic_write	= palmas_i2c_write_u8,
-	.gpio_en = 0,
-};
-
-struct vcores_data omap5430_volts = {
-	.mpu.value = VDD_MPU,
-	.mpu.addr = SMPS_REG_ADDR_12_MPU,
-	.mpu.pmic = &palmas,
-
-	.core.value = VDD_CORE,
-	.core.addr = SMPS_REG_ADDR_8_CORE,
-	.core.pmic = &palmas,
-
-	.mm.value = VDD_MM,
-	.mm.addr = SMPS_REG_ADDR_45_IVA,
-	.mm.pmic = &palmas,
-};
-
-struct vcores_data omap5430_volts_es2 = {
-	.mpu.value = VDD_MPU_ES2,
-	.mpu.addr = SMPS_REG_ADDR_12_MPU,
-	.mpu.pmic = &palmas,
-	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
-	.core.value = VDD_CORE_ES2,
-	.core.addr = SMPS_REG_ADDR_8_CORE,
-	.core.pmic = &palmas,
-
-	.mm.value = VDD_MM_ES2,
-	.mm.addr = SMPS_REG_ADDR_45_IVA,
-	.mm.pmic = &palmas,
-	.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
-};
-
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_basic_clocks(void)
-{
-	u32 const clk_domains_essential[] = {
-		(*prcm)->cm_l4per_clkstctrl,
-		(*prcm)->cm_l3init_clkstctrl,
-		(*prcm)->cm_memif_clkstctrl,
-		(*prcm)->cm_l4cfg_clkstctrl,
-#ifdef CONFIG_DRIVER_TI_CPSW
-		(*prcm)->cm_gmac_clkstctrl,
-#endif
-		0
-	};
-
-	u32 const clk_modules_hw_auto_essential[] = {
-		(*prcm)->cm_l3_gpmc_clkctrl,
-		(*prcm)->cm_memif_emif_1_clkctrl,
-		(*prcm)->cm_memif_emif_2_clkctrl,
-		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
-		(*prcm)->cm_wkup_gpio1_clkctrl,
-		(*prcm)->cm_l4per_gpio2_clkctrl,
-		(*prcm)->cm_l4per_gpio3_clkctrl,
-		(*prcm)->cm_l4per_gpio4_clkctrl,
-		(*prcm)->cm_l4per_gpio5_clkctrl,
-		(*prcm)->cm_l4per_gpio6_clkctrl,
-		(*prcm)->cm_l4per_gpio7_clkctrl,
-		(*prcm)->cm_l4per_gpio8_clkctrl,
-		0
-	};
-
-	u32 const clk_modules_explicit_en_essential[] = {
-		(*prcm)->cm_wkup_gptimer1_clkctrl,
-		(*prcm)->cm_l3init_hsmmc1_clkctrl,
-		(*prcm)->cm_l3init_hsmmc2_clkctrl,
-		(*prcm)->cm_l4per_gptimer2_clkctrl,
-		(*prcm)->cm_wkup_wdtimer2_clkctrl,
-		(*prcm)->cm_l4per_uart3_clkctrl,
-		(*prcm)->cm_l4per_i2c1_clkctrl,
-#ifdef CONFIG_DRIVER_TI_CPSW
-		(*prcm)->cm_gmac_gmac_clkctrl,
-#endif
-
-#ifdef CONFIG_TI_QSPI
-		(*prcm)->cm_l4per_qspi_clkctrl,
-#endif
-		0
-	};
-
-	/* Enable optional additional functional clock for GPIO4 */
-	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
-			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
-	/* Enable 96 MHz clock for MMC1 & MMC2 */
-	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
-			HSMMC_CLKCTRL_CLKSEL_MASK);
-	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
-			HSMMC_CLKCTRL_CLKSEL_MASK);
-
-	/* Set the correct clock dividers for mmc */
-	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
-			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
-			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-
-	/* Select 32KHz clock as the source of GPTIMER1 */
-	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
-			GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
-	do_enable_clocks(clk_domains_essential,
-			 clk_modules_hw_auto_essential,
-			 clk_modules_explicit_en_essential,
-			 1);
-
-#ifdef CONFIG_TI_QSPI
-	setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
-#endif
-
-	/* Enable SCRM OPT clocks for PER and CORE dpll */
-	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
-			OPTFCLKEN_SCRM_PER_MASK);
-	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
-			OPTFCLKEN_SCRM_CORE_MASK);
-}
-
-void enable_basic_uboot_clocks(void)
-{
-	u32 const clk_domains_essential[] = {
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-		(*prcm)->cm_ipu_clkstctrl,
-#endif
-		0
-	};
-
-	u32 const clk_modules_hw_auto_essential[] = {
-		(*prcm)->cm_l3init_hsusbtll_clkctrl,
-		0
-	};
-
-	u32 const clk_modules_explicit_en_essential[] = {
-		(*prcm)->cm_l4per_mcspi1_clkctrl,
-		(*prcm)->cm_l4per_i2c2_clkctrl,
-		(*prcm)->cm_l4per_i2c3_clkctrl,
-		(*prcm)->cm_l4per_i2c4_clkctrl,
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-		(*prcm)->cm_ipu_i2c5_clkctrl,
-#else
-		(*prcm)->cm_l4per_i2c5_clkctrl,
-#endif
-		(*prcm)->cm_l3init_hsusbhost_clkctrl,
-		(*prcm)->cm_l3init_fsusb_clkctrl,
-		0
-	};
-	do_enable_clocks(clk_domains_essential,
-			 clk_modules_hw_auto_essential,
-			 clk_modules_explicit_en_essential,
-			 1);
-}
-
-#ifdef CONFIG_TI_EDMA3
-void enable_edma3_clocks(void)
-{
-	u32 const clk_domains_edma3[] = {
-		0
-	};
-
-	u32 const clk_modules_hw_auto_edma3[] = {
-		(*prcm)->cm_l3main1_tptc1_clkctrl,
-		(*prcm)->cm_l3main1_tptc2_clkctrl,
-		0
-	};
-
-	u32 const clk_modules_explicit_en_edma3[] = {
-		0
-	};
-
-	do_enable_clocks(clk_domains_edma3,
-			 clk_modules_hw_auto_edma3,
-			 clk_modules_explicit_en_edma3,
-			 1);
-}
-
-void disable_edma3_clocks(void)
-{
-	u32 const clk_domains_edma3[] = {
-		0
-	};
-
-	u32 const clk_modules_disable_edma3[] = {
-		(*prcm)->cm_l3main1_tptc1_clkctrl,
-		(*prcm)->cm_l3main1_tptc2_clkctrl,
-		0
-	};
-
-	do_disable_clocks(clk_domains_edma3,
-			  clk_modules_disable_edma3,
-			  1);
-}
-#endif
-
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
-void enable_usb_clocks(int index)
-{
-	u32 cm_l3init_usb_otg_ss_clkctrl = 0;
-
-	if (index == 0) {
-		cm_l3init_usb_otg_ss_clkctrl =
-			(*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
-		/* Enable 960 MHz clock for dwc3 */
-		setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
-			     OPTFCLKEN_REFCLK960M);
-
-		/* Enable 32 KHz clock for USB_PHY1 */
-		setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
-			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
-		/* Enable 32 KHz clock for USB_PHY3 */
-		if (is_dra7xx())
-			setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
-				     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-	} else if (index == 1) {
-		cm_l3init_usb_otg_ss_clkctrl =
-			(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
-		/* Enable 960 MHz clock for dwc3 */
-		setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
-			     OPTFCLKEN_REFCLK960M);
-
-		/* Enable 32 KHz clock for dwc3 */
-		setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
-			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
-		/* Enable 60 MHz clock for USB2PHY2 */
-		setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
-			     L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
-	}
-
-	u32 const clk_domains_usb[] = {
-		0
-	};
-
-	u32 const clk_modules_hw_auto_usb[] = {
-		(*prcm)->cm_l3init_ocp2scp1_clkctrl,
-		cm_l3init_usb_otg_ss_clkctrl,
-		0
-	};
-
-	u32 const clk_modules_explicit_en_usb[] = {
-		0
-	};
-
-	do_enable_clocks(clk_domains_usb,
-			 clk_modules_hw_auto_usb,
-			 clk_modules_explicit_en_usb,
-			 1);
-}
-
-void disable_usb_clocks(int index)
-{
-	u32 cm_l3init_usb_otg_ss_clkctrl = 0;
-
-	if (index == 0) {
-		cm_l3init_usb_otg_ss_clkctrl =
-			(*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
-		/* Disable 960 MHz clock for dwc3 */
-		clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
-			     OPTFCLKEN_REFCLK960M);
-
-		/* Disable 32 KHz clock for USB_PHY1 */
-		clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
-			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
-		/* Disable 32 KHz clock for USB_PHY3 */
-		if (is_dra7xx())
-			clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
-				     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-	} else if (index == 1) {
-		cm_l3init_usb_otg_ss_clkctrl =
-			(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
-		/* Disable 960 MHz clock for dwc3 */
-		clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
-			     OPTFCLKEN_REFCLK960M);
-
-		/* Disable 32 KHz clock for dwc3 */
-		clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
-			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
-		/* Disable 60 MHz clock for USB2PHY2 */
-		clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
-			     L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
-	}
-
-	u32 const clk_domains_usb[] = {
-		0
-	};
-
-	u32 const clk_modules_disable[] = {
-		(*prcm)->cm_l3init_ocp2scp1_clkctrl,
-		cm_l3init_usb_otg_ss_clkctrl,
-		0
-	};
-
-	do_disable_clocks(clk_domains_usb,
-			  clk_modules_disable,
-			  1);
-}
-#endif
-
-const struct ctrl_ioregs ioregs_omap5430 = {
-	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
-	.ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
-	.ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
-	.ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
-};
-
-const struct ctrl_ioregs ioregs_omap5432_es1 = {
-	.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
-	.ctrl_lpddr2ch = 0x0,
-	.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
-	.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
-	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
-	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
-	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
-	.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-};
-
-const struct ctrl_ioregs ioregs_omap5432_es2 = {
-	.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
-	.ctrl_lpddr2ch = 0x0,
-	.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
-	.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
-	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
-	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
-	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
-	.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-};
-
-const struct ctrl_ioregs ioregs_dra7xx_es1 = {
-	.ctrl_ddrch = 0x40404040,
-	.ctrl_lpddr2ch = 0x40404040,
-	.ctrl_ddr3ch = 0x80808080,
-	.ctrl_ddrio_0 = 0x00094A40,
-	.ctrl_ddrio_1 = 0x04A52000,
-	.ctrl_ddrio_2 = 0x84210000,
-	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
-	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
-	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
-};
-
-const struct ctrl_ioregs ioregs_dra72x_es1 = {
-	.ctrl_ddrch = 0x40404040,
-	.ctrl_lpddr2ch = 0x40404040,
-	.ctrl_ddr3ch = 0x60606080,
-	.ctrl_ddrio_0 = 0x00094A40,
-	.ctrl_ddrio_1 = 0x04A52000,
-	.ctrl_ddrio_2 = 0x84210000,
-	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
-	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
-	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
-};
-
-const struct ctrl_ioregs ioregs_dra72x_es2 = {
-	.ctrl_ddrch = 0x40404040,
-	.ctrl_lpddr2ch = 0x40404040,
-	.ctrl_ddr3ch = 0x60606060,
-	.ctrl_ddrio_0 = 0x00094A40,
-	.ctrl_ddrio_1 = 0x00000000,
-	.ctrl_ddrio_2 = 0x00000000,
-	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
-	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
-	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
-};
-
-void __weak hw_data_init(void)
-{
-	u32 omap_rev = omap_revision();
-
-	switch (omap_rev) {
-
-	case OMAP5430_ES1_0:
-	case OMAP5432_ES1_0:
-	*prcm = &omap5_es1_prcm;
-	*dplls_data = &omap5_dplls_es1;
-	*omap_vcores = &omap5430_volts;
-	*ctrl = &omap5_ctrl;
-	break;
-
-	case OMAP5430_ES2_0:
-	case OMAP5432_ES2_0:
-	*prcm = &omap5_es2_prcm;
-	*dplls_data = &omap5_dplls_es2;
-	*omap_vcores = &omap5430_volts_es2;
-	*ctrl = &omap5_ctrl;
-	break;
-
-	case DRA752_ES1_0:
-	case DRA752_ES1_1:
-	case DRA752_ES2_0:
-	*prcm = &dra7xx_prcm;
-	*dplls_data = &dra7xx_dplls;
-	*ctrl = &dra7xx_ctrl;
-	break;
-
-	case DRA722_ES1_0:
-	case DRA722_ES2_0:
-	*prcm = &dra7xx_prcm;
-	*dplls_data = &dra72x_dplls;
-	*ctrl = &dra7xx_ctrl;
-	break;
-
-	default:
-		printf("\n INVALID OMAP REVISION ");
-	}
-}
-
-void get_ioregs(const struct ctrl_ioregs **regs)
-{
-	u32 omap_rev = omap_revision();
-
-	switch (omap_rev) {
-	case OMAP5430_ES1_0:
-	case OMAP5430_ES2_0:
-		*regs = &ioregs_omap5430;
-		break;
-	case OMAP5432_ES1_0:
-		*regs = &ioregs_omap5432_es1;
-		break;
-	case OMAP5432_ES2_0:
-		*regs = &ioregs_omap5432_es2;
-		break;
-	case DRA752_ES1_0:
-	case DRA752_ES1_1:
-	case DRA752_ES2_0:
-		*regs = &ioregs_dra7xx_es1;
-		break;
-	case DRA722_ES1_0:
-		*regs = &ioregs_dra72x_es1;
-		break;
-	case DRA722_ES2_0:
-		*regs = &ioregs_dra72x_es2;
-		break;
-
-	default:
-		printf("\n INVALID OMAP REVISION ");
-	}
-}
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
deleted file mode 100644
index e3ac8bb..0000000
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- *
- * Functions for omap5 based boards.
- *
- * (C) Copyright 2011
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *	Aneesh V	<aneesh@ti.com>
- *	Steve Sakoman	<steve@sakoman.com>
- *	Sricharan	<r.sricharan@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <asm/armv7.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clock.h>
-#include <linux/sizes.h>
-#include <asm/utils.h>
-#include <asm/arch/gpio.h>
-#include <asm/emif.h>
-#include <asm/omap_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
-
-#ifndef CONFIG_DM_GPIO
-static struct gpio_bank gpio_bank_54xx[8] = {
-	{ (void *)OMAP54XX_GPIO1_BASE },
-	{ (void *)OMAP54XX_GPIO2_BASE },
-	{ (void *)OMAP54XX_GPIO3_BASE },
-	{ (void *)OMAP54XX_GPIO4_BASE },
-	{ (void *)OMAP54XX_GPIO5_BASE },
-	{ (void *)OMAP54XX_GPIO6_BASE },
-	{ (void *)OMAP54XX_GPIO7_BASE },
-	{ (void *)OMAP54XX_GPIO8_BASE },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
-#endif
-
-void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
-{
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
-	for (i = 0; i < size; i++, pad++)
-		writel(pad->val, base + pad->offset);
-}
-
-#ifdef CONFIG_SPL_BUILD
-/* LPDDR2 specific IO settings */
-static void io_settings_lpddr2(void)
-{
-	const struct ctrl_ioregs *ioregs;
-
-	get_ioregs(&ioregs);
-	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
-	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
-	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
-	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
-	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
-	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
-	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
-	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
-	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
-}
-
-/* DDR3 specific IO settings */
-static void io_settings_ddr3(void)
-{
-	u32 io_settings = 0;
-	const struct ctrl_ioregs *ioregs;
-
-	get_ioregs(&ioregs);
-	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
-	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
-	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
-
-	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
-	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
-	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
-
-	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
-	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
-
-	if (!is_dra7xx()) {
-		writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
-		writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
-	}
-
-	/* omap5432 does not use lpddr2 */
-	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
-
-	writel(ioregs->ctrl_emif_sdram_config_ext,
-	       (*ctrl)->control_emif1_sdram_config_ext);
-	if (!is_dra72x())
-		writel(ioregs->ctrl_emif_sdram_config_ext,
-		       (*ctrl)->control_emif2_sdram_config_ext);
-
-	if (is_omap54xx()) {
-		/* Disable DLL select */
-		io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
-							& 0xFFEFFFFF);
-		writel(io_settings,
-			(*ctrl)->control_port_emif1_sdram_config);
-
-		io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
-							& 0xFFEFFFFF);
-		writel(io_settings,
-			(*ctrl)->control_port_emif2_sdram_config);
-	} else {
-		writel(ioregs->ctrl_ddr_ctrl_ext_0,
-				(*ctrl)->control_ddr_control_ext_0);
-	}
-}
-
-/*
- * Some tuning of IOs for optimal power and performance
- */
-void do_io_settings(void)
-{
-	u32 io_settings = 0, mask = 0;
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
-	/* Impedance settings EMMC, C2C 1,2, hsi2 */
-	mask = (ds_mask << 2) | (ds_mask << 8) |
-		(ds_mask << 16) | (ds_mask << 18);
-	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
-				(~mask);
-	io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
-			(ds_45_ohm << 18) | (ds_60_ohm << 2);
-	writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
-
-	/* Impedance settings Mcspi2 */
-	mask = (ds_mask << 30);
-	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
-			(~mask);
-	io_settings |= (ds_60_ohm << 30);
-	writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
-
-	/* Impedance settings C2C 3,4 */
-	mask = (ds_mask << 14) | (ds_mask << 16);
-	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
-			(~mask);
-	io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
-	writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
-
-	/* Slew rate settings EMMC, C2C 1,2 */
-	mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
-	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
-			(~mask);
-	io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
-	writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
-
-	/* Slew rate settings hsi2, Mcspi2 */
-	mask = (sc_mask << 24) | (sc_mask << 28);
-	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
-			(~mask);
-	io_settings |= (sc_fast << 28) | (sc_fast << 24);
-	writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
-
-	/* Slew rate settings C2C 3,4 */
-	mask = (sc_mask << 16) | (sc_mask << 18);
-	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
-			(~mask);
-	io_settings |= (sc_na << 16) | (sc_na << 18);
-	writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
-
-	/* impedance and slew rate settings for usb */
-	mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
-		(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
-	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
-			(~mask);
-	io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
-		       (ds_60_ohm << 23) | (sc_fast << 20) |
-		       (sc_fast << 17) | (sc_fast << 14);
-	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
-
-	if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
-		io_settings_lpddr2();
-	else
-		io_settings_ddr3();
-}
-
-static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
-	{0x45, 0x1},	/* 12 MHz   */
-	{-1, -1},	/* 13 MHz   */
-	{0x63, 0x2},	/* 16.8 MHz */
-	{0x57, 0x2},	/* 19.2 MHz */
-	{0x20, 0x1},	/* 26 MHz   */
-	{-1, -1},	/* 27 MHz   */
-	{0x41, 0x3}	/* 38.4 MHz */
-};
-
-void srcomp_enable(void)
-{
-	u32 srcomp_value, mul_factor, div_factor, clk_val, i;
-	u32 sysclk_ind	= get_sys_clk_index();
-	u32 omap_rev	= omap_revision();
-
-	if (!is_omap54xx())
-		return;
-
-	mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
-	div_factor = srcomp_parameters[sysclk_ind].divide_factor;
-
-	for (i = 0; i < 4; i++) {
-		srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
-		srcomp_value &=
-			~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
-		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
-			(div_factor << DIVIDE_FACTOR_XS_SHIFT);
-		writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
-	}
-
-	if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
-		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
-		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
-		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
-
-		for (i = 0; i < 4; i++) {
-			srcomp_value =
-				readl((*ctrl)->control_srcomp_north_side + i*4);
-			srcomp_value &= ~PWRDWN_XS_MASK;
-			writel(srcomp_value,
-			       (*ctrl)->control_srcomp_north_side + i*4);
-
-			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
-				& SRCODE_READ_XS_MASK) >>
-				SRCODE_READ_XS_SHIFT) == 0)
-				;
-
-			srcomp_value =
-				readl((*ctrl)->control_srcomp_north_side + i*4);
-			srcomp_value &= ~OVERRIDE_XS_MASK;
-			writel(srcomp_value,
-			       (*ctrl)->control_srcomp_north_side + i*4);
-		}
-	} else {
-		srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
-		srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
-				  DIVIDE_FACTOR_XS_MASK);
-		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
-				(div_factor << DIVIDE_FACTOR_XS_SHIFT);
-		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
-
-		for (i = 0; i < 4; i++) {
-			srcomp_value =
-				readl((*ctrl)->control_srcomp_north_side + i*4);
-			srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
-			writel(srcomp_value,
-			       (*ctrl)->control_srcomp_north_side + i*4);
-
-			srcomp_value =
-				readl((*ctrl)->control_srcomp_north_side + i*4);
-			srcomp_value &= ~OVERRIDE_XS_MASK;
-			writel(srcomp_value,
-			       (*ctrl)->control_srcomp_north_side + i*4);
-		}
-
-		srcomp_value =
-			readl((*ctrl)->control_srcomp_east_side_wkup);
-		srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
-		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
-
-		srcomp_value =
-			readl((*ctrl)->control_srcomp_east_side_wkup);
-		srcomp_value &= ~OVERRIDE_XS_MASK;
-		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
-
-		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
-		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
-		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
-
-		clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
-		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
-		writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
-
-		for (i = 0; i < 4; i++) {
-			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
-				& SRCODE_READ_XS_MASK) >>
-				SRCODE_READ_XS_SHIFT) == 0)
-				;
-
-			srcomp_value =
-				readl((*ctrl)->control_srcomp_north_side + i*4);
-			srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
-			writel(srcomp_value,
-			       (*ctrl)->control_srcomp_north_side + i*4);
-		}
-
-		while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
-			SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
-			;
-
-		srcomp_value =
-			readl((*ctrl)->control_srcomp_east_side_wkup);
-		srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
-		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
-	}
-}
-#endif
-
-void config_data_eye_leveling_samples(u32 emif_base)
-{
-	const struct ctrl_ioregs *ioregs;
-
-	get_ioregs(&ioregs);
-
-	/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
-	if (emif_base == EMIF1_BASE)
-		writel(ioregs->ctrl_emif_sdram_config_ext_final,
-		       (*ctrl)->control_emif1_sdram_config_ext);
-	else if (emif_base == EMIF2_BASE)
-		writel(ioregs->ctrl_emif_sdram_config_ext_final,
-		       (*ctrl)->control_emif2_sdram_config_ext);
-}
-
-void init_cpu_configuration(void)
-{
-	u32 l2actlr;
-
-	asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
-	/*
-	 * L2ACTLR: Ensure to enable the following:
-	 * 3: Disable clean/evict push to external
-	 * 4: Disable WriteUnique and WriteLineUnique transactions from master
-	 * 8: Disable DVM/CMO message broadcast
-	 */
-	l2actlr |= 0x118;
-	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
-}
-
-void init_omap_revision(void)
-{
-	/*
-	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
-	 * Also, ES1 and ES2 have different ARM revisions
-	 * So use ARM revision for identification
-	 */
-	unsigned int rev = cortex_rev();
-
-	switch (readl(CONTROL_ID_CODE)) {
-	case OMAP5430_CONTROL_ID_CODE_ES1_0:
-		*omap_si_rev = OMAP5430_ES1_0;
-		if (rev == MIDR_CORTEX_A15_R2P2)
-			*omap_si_rev = OMAP5430_ES2_0;
-		break;
-	case OMAP5432_CONTROL_ID_CODE_ES1_0:
-		*omap_si_rev = OMAP5432_ES1_0;
-		if (rev == MIDR_CORTEX_A15_R2P2)
-			*omap_si_rev = OMAP5432_ES2_0;
-		break;
-	case OMAP5430_CONTROL_ID_CODE_ES2_0:
-		*omap_si_rev = OMAP5430_ES2_0;
-		break;
-	case OMAP5432_CONTROL_ID_CODE_ES2_0:
-		*omap_si_rev = OMAP5432_ES2_0;
-		break;
-	case DRA752_CONTROL_ID_CODE_ES1_0:
-		*omap_si_rev = DRA752_ES1_0;
-		break;
-	case DRA752_CONTROL_ID_CODE_ES1_1:
-		*omap_si_rev = DRA752_ES1_1;
-		break;
-	case DRA752_CONTROL_ID_CODE_ES2_0:
-		*omap_si_rev = DRA752_ES2_0;
-		break;
-	case DRA722_CONTROL_ID_CODE_ES1_0:
-		*omap_si_rev = DRA722_ES1_0;
-		break;
-	case DRA722_CONTROL_ID_CODE_ES2_0:
-		*omap_si_rev = DRA722_ES2_0;
-		break;
-	default:
-		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
-	}
-	init_cpu_configuration();
-}
-
-void omap_die_id(unsigned int *die_id)
-{
-	die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
-	die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
-	die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
-	die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
-}
-
-void reset_cpu(ulong ignored)
-{
-	u32 omap_rev = omap_revision();
-
-	/*
-	 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
-	 * So use cold reset in case instead.
-	 */
-	if (omap_rev == OMAP5430_ES1_0)
-		writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
-	else
-		writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
-}
-
-u32 warm_reset(void)
-{
-	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
-}
-
-void setup_warmreset_time(void)
-{
-	u32 rst_time, rst_val;
-
-#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
-	rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
-#else
-	rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
-#endif
-	rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
-
-	if (rst_time > RSTTIME1_MASK)
-		rst_time = RSTTIME1_MASK;
-
-	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
-	rst_val |= rst_time;
-	writel(rst_val, (*prcm)->prm_rsttime);
-}
-
-void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
-				 u32 cpu_rev_comb, u32 cpu_variant,
-				 u32 cpu_rev)
-{
-	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
-}
-
-void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
-			  u32 cpu_variant, u32 cpu_rev)
-{
-
-#ifdef CONFIG_ARM_ERRATA_801819
-	/*
-	 * DRA72x processors are uniprocessors and DONOT have
-	 * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
-	 * Extensions) Hence the erratum workaround is not applicable for
-	 * DRA72x processors.
-	 */
-	if (is_dra72x())
-		acr &= ~((0x3 << 23) | (0x3 << 25));
-#endif
-	omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
-}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
deleted file mode 100644
index b5f1d70..0000000
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ /dev/null
@@ -1,1024 +0,0 @@
-/*
- *
- * HW regs data for OMAP5 Soc
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/omap_common.h>
-#include <asm/io.h>
-
-struct prcm_regs const omap5_es1_prcm = {
-	/* cm1.ckgen */
-	.cm_clksel_core = 0x4a004100,
-	.cm_clksel_abe = 0x4a004108,
-	.cm_dll_ctrl = 0x4a004110,
-	.cm_clkmode_dpll_core = 0x4a004120,
-	.cm_idlest_dpll_core = 0x4a004124,
-	.cm_autoidle_dpll_core = 0x4a004128,
-	.cm_clksel_dpll_core = 0x4a00412c,
-	.cm_div_m2_dpll_core = 0x4a004130,
-	.cm_div_m3_dpll_core = 0x4a004134,
-	.cm_div_h11_dpll_core = 0x4a004138,
-	.cm_div_h12_dpll_core = 0x4a00413c,
-	.cm_div_h13_dpll_core = 0x4a004140,
-	.cm_div_h14_dpll_core = 0x4a004144,
-	.cm_ssc_deltamstep_dpll_core = 0x4a004148,
-	.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
-	.cm_emu_override_dpll_core = 0x4a004150,
-	.cm_div_h22_dpllcore = 0x4a004154,
-	.cm_div_h23_dpll_core = 0x4a004158,
-	.cm_clkmode_dpll_mpu = 0x4a004160,
-	.cm_idlest_dpll_mpu = 0x4a004164,
-	.cm_autoidle_dpll_mpu = 0x4a004168,
-	.cm_clksel_dpll_mpu = 0x4a00416c,
-	.cm_div_m2_dpll_mpu = 0x4a004170,
-	.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
-	.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
-	.cm_bypclk_dpll_mpu = 0x4a00419c,
-	.cm_clkmode_dpll_iva = 0x4a0041a0,
-	.cm_idlest_dpll_iva = 0x4a0041a4,
-	.cm_autoidle_dpll_iva = 0x4a0041a8,
-	.cm_clksel_dpll_iva = 0x4a0041ac,
-	.cm_div_h11_dpll_iva = 0x4a0041b8,
-	.cm_div_h12_dpll_iva = 0x4a0041bc,
-	.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
-	.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
-	.cm_bypclk_dpll_iva = 0x4a0041dc,
-	.cm_clkmode_dpll_abe = 0x4a0041e0,
-	.cm_idlest_dpll_abe = 0x4a0041e4,
-	.cm_autoidle_dpll_abe = 0x4a0041e8,
-	.cm_clksel_dpll_abe = 0x4a0041ec,
-	.cm_div_m2_dpll_abe = 0x4a0041f0,
-	.cm_div_m3_dpll_abe = 0x4a0041f4,
-	.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
-	.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
-	.cm_clkmode_dpll_ddrphy = 0x4a004220,
-	.cm_idlest_dpll_ddrphy = 0x4a004224,
-	.cm_autoidle_dpll_ddrphy = 0x4a004228,
-	.cm_clksel_dpll_ddrphy = 0x4a00422c,
-	.cm_div_m2_dpll_ddrphy = 0x4a004230,
-	.cm_div_h11_dpll_ddrphy = 0x4a004238,
-	.cm_div_h12_dpll_ddrphy = 0x4a00423c,
-	.cm_div_h13_dpll_ddrphy = 0x4a004240,
-	.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
-	.cm_shadow_freq_config1 = 0x4a004260,
-	.cm_mpu_mpu_clkctrl = 0x4a004320,
-
-	/* cm1.dsp */
-	.cm_dsp_clkstctrl = 0x4a004400,
-	.cm_dsp_dsp_clkctrl = 0x4a004420,
-
-	/* cm1.abe */
-	.cm1_abe_clkstctrl = 0x4a004500,
-	.cm1_abe_l4abe_clkctrl = 0x4a004520,
-	.cm1_abe_aess_clkctrl = 0x4a004528,
-	.cm1_abe_pdm_clkctrl = 0x4a004530,
-	.cm1_abe_dmic_clkctrl = 0x4a004538,
-	.cm1_abe_mcasp_clkctrl = 0x4a004540,
-	.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
-	.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
-	.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
-	.cm1_abe_slimbus_clkctrl = 0x4a004560,
-	.cm1_abe_timer5_clkctrl = 0x4a004568,
-	.cm1_abe_timer6_clkctrl = 0x4a004570,
-	.cm1_abe_timer7_clkctrl = 0x4a004578,
-	.cm1_abe_timer8_clkctrl = 0x4a004580,
-	.cm1_abe_wdt3_clkctrl = 0x4a004588,
-
-	/* cm2.ckgen */
-	.cm_clksel_mpu_m3_iss_root = 0x4a008100,
-	.cm_clksel_usb_60mhz = 0x4a008104,
-	.cm_scale_fclk = 0x4a008108,
-	.cm_core_dvfs_perf1 = 0x4a008110,
-	.cm_core_dvfs_perf2 = 0x4a008114,
-	.cm_core_dvfs_perf3 = 0x4a008118,
-	.cm_core_dvfs_perf4 = 0x4a00811c,
-	.cm_core_dvfs_current = 0x4a008124,
-	.cm_iva_dvfs_perf_tesla = 0x4a008128,
-	.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
-	.cm_iva_dvfs_perf_abe = 0x4a008130,
-	.cm_iva_dvfs_current = 0x4a008138,
-	.cm_clkmode_dpll_per = 0x4a008140,
-	.cm_idlest_dpll_per = 0x4a008144,
-	.cm_autoidle_dpll_per = 0x4a008148,
-	.cm_clksel_dpll_per = 0x4a00814c,
-	.cm_div_m2_dpll_per = 0x4a008150,
-	.cm_div_m3_dpll_per = 0x4a008154,
-	.cm_div_h11_dpll_per = 0x4a008158,
-	.cm_div_h12_dpll_per = 0x4a00815c,
-	.cm_div_h14_dpll_per = 0x4a008164,
-	.cm_ssc_deltamstep_dpll_per = 0x4a008168,
-	.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
-	.cm_emu_override_dpll_per = 0x4a008170,
-	.cm_clkmode_dpll_usb = 0x4a008180,
-	.cm_idlest_dpll_usb = 0x4a008184,
-	.cm_autoidle_dpll_usb = 0x4a008188,
-	.cm_clksel_dpll_usb = 0x4a00818c,
-	.cm_div_m2_dpll_usb = 0x4a008190,
-	.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
-	.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
-	.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
-	.cm_clkmode_dpll_unipro = 0x4a0081c0,
-	.cm_idlest_dpll_unipro = 0x4a0081c4,
-	.cm_autoidle_dpll_unipro = 0x4a0081c8,
-	.cm_clksel_dpll_unipro = 0x4a0081cc,
-	.cm_div_m2_dpll_unipro = 0x4a0081d0,
-	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
-	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
-
-	/* cm2.core */
-	.cm_coreaon_bandgap_clkctrl = 0x4a008648,
-	.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
-	.cm_l3_1_clkstctrl = 0x4a008700,
-	.cm_l3_1_dynamicdep = 0x4a008708,
-	.cm_l3_1_l3_1_clkctrl = 0x4a008720,
-	.cm_l3_2_clkstctrl = 0x4a008800,
-	.cm_l3_2_dynamicdep = 0x4a008808,
-	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
-	.cm_l3_gpmc_clkctrl = 0x4a008828,
-	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
-	.cm_mpu_m3_clkstctrl = 0x4a008900,
-	.cm_mpu_m3_staticdep = 0x4a008904,
-	.cm_mpu_m3_dynamicdep = 0x4a008908,
-	.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
-	.cm_sdma_clkstctrl = 0x4a008a00,
-	.cm_sdma_staticdep = 0x4a008a04,
-	.cm_sdma_dynamicdep = 0x4a008a08,
-	.cm_sdma_sdma_clkctrl = 0x4a008a20,
-	.cm_memif_clkstctrl = 0x4a008b00,
-	.cm_memif_dmm_clkctrl = 0x4a008b20,
-	.cm_memif_emif_fw_clkctrl = 0x4a008b28,
-	.cm_memif_emif_1_clkctrl = 0x4a008b30,
-	.cm_memif_emif_2_clkctrl = 0x4a008b38,
-	.cm_memif_dll_clkctrl = 0x4a008b40,
-	.cm_memif_emif_h1_clkctrl = 0x4a008b50,
-	.cm_memif_emif_h2_clkctrl = 0x4a008b58,
-	.cm_memif_dll_h_clkctrl = 0x4a008b60,
-	.cm_c2c_clkstctrl = 0x4a008c00,
-	.cm_c2c_staticdep = 0x4a008c04,
-	.cm_c2c_dynamicdep = 0x4a008c08,
-	.cm_c2c_sad2d_clkctrl = 0x4a008c20,
-	.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
-	.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
-	.cm_l4cfg_clkstctrl = 0x4a008d00,
-	.cm_l4cfg_dynamicdep = 0x4a008d08,
-	.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
-	.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
-	.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
-	.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
-	.cm_l3instr_clkstctrl = 0x4a008e00,
-	.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
-	.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
-	.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
-
-	/* cm2.ivahd */
-	.cm_ivahd_clkstctrl = 0x4a008f00,
-	.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
-	.cm_ivahd_sl2_clkctrl = 0x4a008f28,
-
-	/* cm2.cam */
-	.cm_cam_clkstctrl = 0x4a009000,
-	.cm_cam_iss_clkctrl = 0x4a009020,
-	.cm_cam_fdif_clkctrl = 0x4a009028,
-
-	/* cm2.dss */
-	.cm_dss_clkstctrl = 0x4a009100,
-	.cm_dss_dss_clkctrl = 0x4a009120,
-
-	/* cm2.sgx */
-	.cm_sgx_clkstctrl = 0x4a009200,
-	.cm_sgx_sgx_clkctrl = 0x4a009220,
-
-	/* cm2.l3init */
-	.cm_l3init_clkstctrl = 0x4a009300,
-	.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
-	.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
-	.cm_l3init_hsi_clkctrl = 0x4a009338,
-	.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
-	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
-	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
-	.cm_l3init_p1500_clkctrl = 0x4a009378,
-	.cm_l3init_sata_clkctrl = 0x4a009388,
-	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
-	.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
-	.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
-
-	/* cm2.l4per */
-	.cm_l4per_clkstctrl = 0x4a009400,
-	.cm_l4per_dynamicdep = 0x4a009408,
-	.cm_l4per_adc_clkctrl = 0x4a009420,
-	.cm_l4per_gptimer10_clkctrl = 0x4a009428,
-	.cm_l4per_gptimer11_clkctrl = 0x4a009430,
-	.cm_l4per_gptimer2_clkctrl = 0x4a009438,
-	.cm_l4per_gptimer3_clkctrl = 0x4a009440,
-	.cm_l4per_gptimer4_clkctrl = 0x4a009448,
-	.cm_l4per_gptimer9_clkctrl = 0x4a009450,
-	.cm_l4per_elm_clkctrl = 0x4a009458,
-	.cm_l4per_gpio2_clkctrl = 0x4a009460,
-	.cm_l4per_gpio3_clkctrl = 0x4a009468,
-	.cm_l4per_gpio4_clkctrl = 0x4a009470,
-	.cm_l4per_gpio5_clkctrl = 0x4a009478,
-	.cm_l4per_gpio6_clkctrl = 0x4a009480,
-	.cm_l4per_hdq1w_clkctrl = 0x4a009488,
-	.cm_l4per_hecc1_clkctrl = 0x4a009490,
-	.cm_l4per_hecc2_clkctrl = 0x4a009498,
-	.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
-	.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
-	.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
-	.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
-	.cm_l4per_l4per_clkctrl = 0x4a0094c0,
-	.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
-	.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
-	.cm_l4per_mgate_clkctrl = 0x4a0094e8,
-	.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
-	.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
-	.cm_l4per_mcspi3_clkctrl = 0x4a009500,
-	.cm_l4per_mcspi4_clkctrl = 0x4a009508,
-	.cm_l4per_gpio7_clkctrl = 0x4a009510,
-	.cm_l4per_gpio8_clkctrl = 0x4a009518,
-	.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
-	.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
-	.cm_l4per_msprohg_clkctrl = 0x4a009530,
-	.cm_l4per_slimbus2_clkctrl = 0x4a009538,
-	.cm_l4per_uart1_clkctrl = 0x4a009540,
-	.cm_l4per_uart2_clkctrl = 0x4a009548,
-	.cm_l4per_uart3_clkctrl = 0x4a009550,
-	.cm_l4per_uart4_clkctrl = 0x4a009558,
-	.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
-	.cm_l4per_i2c5_clkctrl = 0x4a009568,
-	.cm_l4per_uart5_clkctrl = 0x4a009570,
-	.cm_l4per_uart6_clkctrl = 0x4a009578,
-	.cm_l4sec_clkstctrl = 0x4a009580,
-	.cm_l4sec_staticdep = 0x4a009584,
-	.cm_l4sec_dynamicdep = 0x4a009588,
-	.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
-	.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
-	.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
-	.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
-	.cm_l4sec_rng_clkctrl = 0x4a0095c0,
-	.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
-	.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
-
-	/* l4 wkup regs */
-	.cm_abe_pll_ref_clksel = 0x4ae0610c,
-	.cm_sys_clksel = 0x4ae06110,
-	.cm_wkup_clkstctrl = 0x4ae07800,
-	.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
-	.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
-	.cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
-	.cm_wkup_gpio1_clkctrl = 0x4ae07838,
-	.cm_wkup_gptimer1_clkctrl = 0x4ae07840,
-	.cm_wkup_gptimer12_clkctrl = 0x4ae07848,
-	.cm_wkup_synctimer_clkctrl = 0x4ae07850,
-	.cm_wkup_usim_clkctrl = 0x4ae07858,
-	.cm_wkup_sarram_clkctrl = 0x4ae07860,
-	.cm_wkup_keyboard_clkctrl = 0x4ae07878,
-	.cm_wkup_rtc_clkctrl = 0x4ae07880,
-	.cm_wkup_bandgap_clkctrl = 0x4ae07888,
-	.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
-	.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
-	.prm_rstctrl = 0x4ae07b00,
-	.prm_rstst = 0x4ae07b04,
-	.prm_rsttime = 0x4ae07b08,
-	.prm_vc_val_bypass = 0x4ae07ba0,
-	.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
-	.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
-
-	/* SCRM stuff, used by some boards */
-	.scrm_auxclk0 = 0x4ae0a310,
-	.scrm_auxclk1 = 0x4ae0a314,
-};
-
-struct omap_sys_ctrl_regs const omap5_ctrl = {
-	.control_status				= 0x4A002134,
-	.control_std_fuse_die_id_0		= 0x4A002200,
-	.control_std_fuse_die_id_1		= 0x4A002208,
-	.control_std_fuse_die_id_2		= 0x4A00220C,
-	.control_std_fuse_die_id_3		= 0x4A002210,
-	.control_phy_power_usb 			= 0x4A002370,
-	.control_phy_power_sata			= 0x4A002374,
-	.control_padconf_core_base		= 0x4A002800,
-	.control_paconf_global			= 0x4A002DA0,
-	.control_paconf_mode			= 0x4A002DA4,
-	.control_smart1io_padconf_0		= 0x4A002DA8,
-	.control_smart1io_padconf_1		= 0x4A002DAC,
-	.control_smart1io_padconf_2		= 0x4A002DB0,
-	.control_smart2io_padconf_0		= 0x4A002DB4,
-	.control_smart2io_padconf_1		= 0x4A002DB8,
-	.control_smart2io_padconf_2		= 0x4A002DBC,
-	.control_smart3io_padconf_0		= 0x4A002DC0,
-	.control_smart3io_padconf_1		= 0x4A002DC4,
-	.control_pbias				= 0x4A002E00,
-	.control_i2c_0				= 0x4A002E04,
-	.control_camera_rx			= 0x4A002E08,
-	.control_hdmi_tx_phy			= 0x4A002E0C,
-	.control_uniportm			= 0x4A002E10,
-	.control_dsiphy				= 0x4A002E14,
-	.control_mcbsplp			= 0x4A002E18,
-	.control_usb2phycore			= 0x4A002E1C,
-	.control_hdmi_1				= 0x4A002E20,
-	.control_hsi				= 0x4A002E24,
-	.control_ddr3ch1_0			= 0x4A002E30,
-	.control_ddr3ch2_0			= 0x4A002E34,
-	.control_ddrch1_0			= 0x4A002E38,
-	.control_ddrch1_1			= 0x4A002E3C,
-	.control_ddrch2_0			= 0x4A002E40,
-	.control_ddrch2_1			= 0x4A002E44,
-	.control_lpddr2ch1_0			= 0x4A002E48,
-	.control_lpddr2ch1_1			= 0x4A002E4C,
-	.control_ddrio_0			= 0x4A002E50,
-	.control_ddrio_1			= 0x4A002E54,
-	.control_ddrio_2			= 0x4A002E58,
-	.control_hyst_1				= 0x4A002E5C,
-	.control_usbb_hsic_control		= 0x4A002E60,
-	.control_c2c				= 0x4A002E64,
-	.control_core_control_spare_rw		= 0x4A002E68,
-	.control_core_control_spare_r		= 0x4A002E6C,
-	.control_core_control_spare_r_c0	= 0x4A002E70,
-	.control_srcomp_north_side		= 0x4A002E74,
-	.control_srcomp_south_side		= 0x4A002E78,
-	.control_srcomp_east_side		= 0x4A002E7C,
-	.control_srcomp_west_side		= 0x4A002E80,
-	.control_srcomp_code_latch		= 0x4A002E84,
-	.control_port_emif1_sdram_config	= 0x4AE0C110,
-	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
-	.control_port_emif2_sdram_config	= 0x4AE0C118,
-	.control_emif1_sdram_config_ext		= 0x4AE0C144,
-	.control_emif2_sdram_config_ext		= 0x4AE0C148,
-	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C318,
-	.control_wkup_ldovbb_mm_voltage_ctrl	= 0x4AE0C314,
-	.control_padconf_wkup_base		= 0x4AE0C800,
-	.control_smart1nopmio_padconf_0		= 0x4AE0CDA0,
-	.control_smart1nopmio_padconf_1		= 0x4AE0CDA4,
-	.control_padconf_mode			= 0x4AE0CDA8,
-	.control_xtal_oscillator		= 0x4AE0CDAC,
-	.control_i2c_2				= 0x4AE0CDB0,
-	.control_ckobuffer			= 0x4AE0CDB4,
-	.control_wkup_control_spare_rw		= 0x4AE0CDB8,
-	.control_wkup_control_spare_r		= 0x4AE0CDBC,
-	.control_wkup_control_spare_r_c0	= 0x4AE0CDC0,
-	.control_srcomp_east_side_wkup		= 0x4AE0CDC4,
-	.control_efuse_1			= 0x4AE0CDC8,
-	.control_efuse_2			= 0x4AE0CDCC,
-	.control_efuse_3			= 0x4AE0CDD0,
-	.control_efuse_4			= 0x4AE0CDD4,
-	.control_efuse_5			= 0x4AE0CDD8,
-	.control_efuse_6			= 0x4AE0CDDC,
-	.control_efuse_7			= 0x4AE0CDE0,
-	.control_efuse_8			= 0x4AE0CDE4,
-	.control_efuse_9			= 0x4AE0CDE8,
-	.control_efuse_10			= 0x4AE0CDEC,
-	.control_efuse_11			= 0x4AE0CDF0,
-	.control_efuse_12			= 0x4AE0CDF4,
-	.control_efuse_13			= 0x4AE0CDF8,
-};
-
-struct omap_sys_ctrl_regs const dra7xx_ctrl = {
-	.control_status				= 0x4A002134,
-	.control_phy_power_usb			= 0x4A002370,
-	.control_phy_power_sata			= 0x4A002374,
-	.ctrl_core_sma_sw_0			= 0x4A0023FC,
-	.ctrl_core_sma_sw_1			= 0x4A002534,
-	.control_core_mac_id_0_lo		= 0x4A002514,
-	.control_core_mac_id_0_hi		= 0x4A002518,
-	.control_core_mac_id_1_lo		= 0x4A00251C,
-	.control_core_mac_id_1_hi		= 0x4A002520,
-	.control_core_mmr_lock1			= 0x4A002540,
-	.control_core_mmr_lock2			= 0x4A002544,
-	.control_core_mmr_lock3			= 0x4A002548,
-	.control_core_mmr_lock4			= 0x4A00254C,
-	.control_core_mmr_lock5			= 0x4A002550,
-	.control_core_control_io1		= 0x4A002554,
-	.control_core_control_io2		= 0x4A002558,
-	.control_paconf_global			= 0x4A002DA0,
-	.control_paconf_mode			= 0x4A002DA4,
-	.control_smart1io_padconf_0		= 0x4A002DA8,
-	.control_smart1io_padconf_1		= 0x4A002DAC,
-	.control_smart1io_padconf_2		= 0x4A002DB0,
-	.control_smart2io_padconf_0		= 0x4A002DB4,
-	.control_smart2io_padconf_1		= 0x4A002DB8,
-	.control_smart2io_padconf_2		= 0x4A002DBC,
-	.control_smart3io_padconf_0		= 0x4A002DC0,
-	.control_smart3io_padconf_1		= 0x4A002DC4,
-	.control_pbias				= 0x4A002E00,
-	.control_i2c_0				= 0x4A002E04,
-	.control_camera_rx			= 0x4A002E08,
-	.control_hdmi_tx_phy			= 0x4A002E0C,
-	.control_uniportm			= 0x4A002E10,
-	.control_dsiphy				= 0x4A002E14,
-	.control_mcbsplp			= 0x4A002E18,
-	.control_usb2phycore			= 0x4A002E1C,
-	.control_hdmi_1				= 0x4A002E20,
-	.control_hsi				= 0x4A002E24,
-	.control_ddr3ch1_0			= 0x4A002E30,
-	.control_ddr3ch2_0			= 0x4A002E34,
-	.control_ddrch1_0			= 0x4A002E38,
-	.control_ddrch1_1			= 0x4A002E3C,
-	.control_ddrch2_0			= 0x4A002E40,
-	.control_ddrch2_1			= 0x4A002E44,
-	.control_lpddr2ch1_0			= 0x4A002E48,
-	.control_lpddr2ch1_1			= 0x4A002E4C,
-	.control_ddrio_0			= 0x4A002E50,
-	.control_ddrio_1			= 0x4A002E54,
-	.control_ddrio_2			= 0x4A002E58,
-	.control_hyst_1				= 0x4A002E5C,
-	.control_usbb_hsic_control		= 0x4A002E60,
-	.control_c2c				= 0x4A002E64,
-	.control_core_control_spare_rw		= 0x4A002E68,
-	.control_core_control_spare_r		= 0x4A002E6C,
-	.control_core_control_spare_r_c0	= 0x4A002E70,
-	.control_srcomp_north_side		= 0x4A002E74,
-	.control_srcomp_south_side		= 0x4A002E78,
-	.control_srcomp_east_side		= 0x4A002E7C,
-	.control_srcomp_west_side		= 0x4A002E80,
-	.control_srcomp_code_latch		= 0x4A002E84,
-	.control_ddr_control_ext_0		= 0x4A002E88,
-	.control_padconf_core_base		= 0x4A003400,
-	.control_port_emif1_sdram_config	= 0x4AE0C110,
-	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
-	.control_port_emif2_sdram_config	= 0x4AE0C118,
-	.control_emif1_sdram_config_ext		= 0x4AE0C144,
-	.control_emif2_sdram_config_ext		= 0x4AE0C148,
-	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C158,
-	.control_wkup_ldovbb_iva_voltage_ctrl	= 0x4A002470,
-	.control_wkup_ldovbb_eve_voltage_ctrl	= 0x4A00246C,
-	.control_wkup_ldovbb_gpu_voltage_ctrl	= 0x4AE0C154,
-	.control_std_fuse_die_id_0		= 0x4AE0C200,
-	.control_std_fuse_die_id_1		= 0x4AE0C208,
-	.control_std_fuse_die_id_2		= 0x4AE0C20C,
-	.control_std_fuse_die_id_3		= 0x4AE0C210,
-	.control_padconf_mode			= 0x4AE0C5A0,
-	.control_xtal_oscillator		= 0x4AE0C5A4,
-	.control_i2c_2				= 0x4AE0C5A8,
-	.control_ckobuffer			= 0x4AE0C5AC,
-	.control_wkup_control_spare_rw		= 0x4AE0C5B0,
-	.control_wkup_control_spare_r		= 0x4AE0C5B4,
-	.control_wkup_control_spare_r_c0	= 0x4AE0C5B8,
-	.control_srcomp_east_side_wkup		= 0x4AE0C5BC,
-	.control_efuse_1			= 0x4AE0C5C8,
-	.control_efuse_2			= 0x4AE0C5CC,
-	.control_efuse_3			= 0x4AE0C5D0,
-	.control_efuse_4			= 0x4AE0C5D4,
-	.control_efuse_13			= 0x4AE0C5F0,
-	.iodelay_config_base			= 0x4844A000,
-};
-
-struct prcm_regs const omap5_es2_prcm = {
-	/* cm1.ckgen */
-	.cm_clksel_core = 0x4a004100,
-	.cm_clksel_abe = 0x4a004108,
-	.cm_dll_ctrl = 0x4a004110,
-	.cm_clkmode_dpll_core = 0x4a004120,
-	.cm_idlest_dpll_core = 0x4a004124,
-	.cm_autoidle_dpll_core = 0x4a004128,
-	.cm_clksel_dpll_core = 0x4a00412c,
-	.cm_div_m2_dpll_core = 0x4a004130,
-	.cm_div_m3_dpll_core = 0x4a004134,
-	.cm_div_h11_dpll_core = 0x4a004138,
-	.cm_div_h12_dpll_core = 0x4a00413c,
-	.cm_div_h13_dpll_core = 0x4a004140,
-	.cm_div_h14_dpll_core = 0x4a004144,
-	.cm_ssc_deltamstep_dpll_core = 0x4a004148,
-	.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
-	.cm_div_h21_dpll_core = 0x4a004150,
-	.cm_div_h22_dpllcore = 0x4a004154,
-	.cm_div_h23_dpll_core = 0x4a004158,
-	.cm_div_h24_dpll_core = 0x4a00415c,
-	.cm_clkmode_dpll_mpu = 0x4a004160,
-	.cm_idlest_dpll_mpu = 0x4a004164,
-	.cm_autoidle_dpll_mpu = 0x4a004168,
-	.cm_clksel_dpll_mpu = 0x4a00416c,
-	.cm_div_m2_dpll_mpu = 0x4a004170,
-	.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
-	.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
-	.cm_bypclk_dpll_mpu = 0x4a00419c,
-	.cm_clkmode_dpll_iva = 0x4a0041a0,
-	.cm_idlest_dpll_iva = 0x4a0041a4,
-	.cm_autoidle_dpll_iva = 0x4a0041a8,
-	.cm_clksel_dpll_iva = 0x4a0041ac,
-	.cm_div_h11_dpll_iva = 0x4a0041b8,
-	.cm_div_h12_dpll_iva = 0x4a0041bc,
-	.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
-	.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
-	.cm_bypclk_dpll_iva = 0x4a0041dc,
-	.cm_clkmode_dpll_abe = 0x4a0041e0,
-	.cm_idlest_dpll_abe = 0x4a0041e4,
-	.cm_autoidle_dpll_abe = 0x4a0041e8,
-	.cm_clksel_dpll_abe = 0x4a0041ec,
-	.cm_div_m2_dpll_abe = 0x4a0041f0,
-	.cm_div_m3_dpll_abe = 0x4a0041f4,
-	.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
-	.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
-	.cm_clkmode_dpll_ddrphy = 0x4a004220,
-	.cm_idlest_dpll_ddrphy = 0x4a004224,
-	.cm_autoidle_dpll_ddrphy = 0x4a004228,
-	.cm_clksel_dpll_ddrphy = 0x4a00422c,
-	.cm_div_m2_dpll_ddrphy = 0x4a004230,
-	.cm_div_h11_dpll_ddrphy = 0x4a004238,
-	.cm_div_h12_dpll_ddrphy = 0x4a00423c,
-	.cm_div_h13_dpll_ddrphy = 0x4a004240,
-	.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
-	.cm_shadow_freq_config1 = 0x4a004260,
-	.cm_mpu_mpu_clkctrl = 0x4a004320,
-
-	/* cm1.dsp */
-	.cm_dsp_clkstctrl = 0x4a004400,
-	.cm_dsp_dsp_clkctrl = 0x4a004420,
-
-	/* cm1.abe */
-	.cm1_abe_clkstctrl = 0x4a004500,
-	.cm1_abe_l4abe_clkctrl = 0x4a004520,
-	.cm1_abe_aess_clkctrl = 0x4a004528,
-	.cm1_abe_pdm_clkctrl = 0x4a004530,
-	.cm1_abe_dmic_clkctrl = 0x4a004538,
-	.cm1_abe_mcasp_clkctrl = 0x4a004540,
-	.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
-	.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
-	.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
-	.cm1_abe_slimbus_clkctrl = 0x4a004560,
-	.cm1_abe_timer5_clkctrl = 0x4a004568,
-	.cm1_abe_timer6_clkctrl = 0x4a004570,
-	.cm1_abe_timer7_clkctrl = 0x4a004578,
-	.cm1_abe_timer8_clkctrl = 0x4a004580,
-	.cm1_abe_wdt3_clkctrl = 0x4a004588,
-
-	/* cm2.ckgen */
-	.cm_clksel_mpu_m3_iss_root = 0x4a008100,
-	.cm_clksel_usb_60mhz = 0x4a008104,
-	.cm_scale_fclk = 0x4a008108,
-	.cm_core_dvfs_perf1 = 0x4a008110,
-	.cm_core_dvfs_perf2 = 0x4a008114,
-	.cm_core_dvfs_perf3 = 0x4a008118,
-	.cm_core_dvfs_perf4 = 0x4a00811c,
-	.cm_core_dvfs_current = 0x4a008124,
-	.cm_iva_dvfs_perf_tesla = 0x4a008128,
-	.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
-	.cm_iva_dvfs_perf_abe = 0x4a008130,
-	.cm_iva_dvfs_current = 0x4a008138,
-	.cm_clkmode_dpll_per = 0x4a008140,
-	.cm_idlest_dpll_per = 0x4a008144,
-	.cm_autoidle_dpll_per = 0x4a008148,
-	.cm_clksel_dpll_per = 0x4a00814c,
-	.cm_div_m2_dpll_per = 0x4a008150,
-	.cm_div_m3_dpll_per = 0x4a008154,
-	.cm_div_h11_dpll_per = 0x4a008158,
-	.cm_div_h12_dpll_per = 0x4a00815c,
-	.cm_div_h13_dpll_per = 0x4a008160,
-	.cm_div_h14_dpll_per = 0x4a008164,
-	.cm_ssc_deltamstep_dpll_per = 0x4a008168,
-	.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
-	.cm_emu_override_dpll_per = 0x4a008170,
-	.cm_clkmode_dpll_usb = 0x4a008180,
-	.cm_idlest_dpll_usb = 0x4a008184,
-	.cm_autoidle_dpll_usb = 0x4a008188,
-	.cm_clksel_dpll_usb = 0x4a00818c,
-	.cm_div_m2_dpll_usb = 0x4a008190,
-	.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
-	.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
-	.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
-	.cm_clkmode_dpll_unipro = 0x4a0081c0,
-	.cm_idlest_dpll_unipro = 0x4a0081c4,
-	.cm_autoidle_dpll_unipro = 0x4a0081c8,
-	.cm_clksel_dpll_unipro = 0x4a0081cc,
-	.cm_div_m2_dpll_unipro = 0x4a0081d0,
-	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
-	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
-	.cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640,
-	.cm_coreaon_bandgap_clkctrl = 0x4a008648,
-	.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
-
-	/* cm2.core */
-	.cm_l3_1_clkstctrl = 0x4a008700,
-	.cm_l3_1_dynamicdep = 0x4a008708,
-	.cm_l3_1_l3_1_clkctrl = 0x4a008720,
-	.cm_l3_2_clkstctrl = 0x4a008800,
-	.cm_l3_2_dynamicdep = 0x4a008808,
-	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
-	.cm_l3_gpmc_clkctrl = 0x4a008828,
-	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
-	.cm_mpu_m3_clkstctrl = 0x4a008900,
-	.cm_mpu_m3_staticdep = 0x4a008904,
-	.cm_mpu_m3_dynamicdep = 0x4a008908,
-	.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
-	.cm_sdma_clkstctrl = 0x4a008a00,
-	.cm_sdma_staticdep = 0x4a008a04,
-	.cm_sdma_dynamicdep = 0x4a008a08,
-	.cm_sdma_sdma_clkctrl = 0x4a008a20,
-	.cm_memif_clkstctrl = 0x4a008b00,
-	.cm_memif_dmm_clkctrl = 0x4a008b20,
-	.cm_memif_emif_fw_clkctrl = 0x4a008b28,
-	.cm_memif_emif_1_clkctrl = 0x4a008b30,
-	.cm_memif_emif_2_clkctrl = 0x4a008b38,
-	.cm_memif_dll_clkctrl = 0x4a008b40,
-	.cm_memif_emif_h1_clkctrl = 0x4a008b50,
-	.cm_memif_emif_h2_clkctrl = 0x4a008b58,
-	.cm_memif_dll_h_clkctrl = 0x4a008b60,
-	.cm_c2c_clkstctrl = 0x4a008c00,
-	.cm_c2c_staticdep = 0x4a008c04,
-	.cm_c2c_dynamicdep = 0x4a008c08,
-	.cm_c2c_sad2d_clkctrl = 0x4a008c20,
-	.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
-	.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
-	.cm_l4cfg_clkstctrl = 0x4a008d00,
-	.cm_l4cfg_dynamicdep = 0x4a008d08,
-	.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
-	.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
-	.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
-	.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
-	.cm_l3instr_clkstctrl = 0x4a008e00,
-	.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
-	.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
-	.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
-	.cm_l4per_clkstctrl = 0x4a009000,
-	.cm_l4per_dynamicdep = 0x4a009008,
-	.cm_l4per_adc_clkctrl = 0x4a009020,
-	.cm_l4per_gptimer10_clkctrl = 0x4a009028,
-	.cm_l4per_gptimer11_clkctrl = 0x4a009030,
-	.cm_l4per_gptimer2_clkctrl = 0x4a009038,
-	.cm_l4per_gptimer3_clkctrl = 0x4a009040,
-	.cm_l4per_gptimer4_clkctrl = 0x4a009048,
-	.cm_l4per_gptimer9_clkctrl = 0x4a009050,
-	.cm_l4per_elm_clkctrl = 0x4a009058,
-	.cm_l4per_gpio2_clkctrl = 0x4a009060,
-	.cm_l4per_gpio3_clkctrl = 0x4a009068,
-	.cm_l4per_gpio4_clkctrl = 0x4a009070,
-	.cm_l4per_gpio5_clkctrl = 0x4a009078,
-	.cm_l4per_gpio6_clkctrl = 0x4a009080,
-	.cm_l4per_hdq1w_clkctrl = 0x4a009088,
-	.cm_l4per_hecc1_clkctrl = 0x4a009090,
-	.cm_l4per_hecc2_clkctrl = 0x4a009098,
-	.cm_l4per_i2c1_clkctrl = 0x4a0090a0,
-	.cm_l4per_i2c2_clkctrl = 0x4a0090a8,
-	.cm_l4per_i2c3_clkctrl = 0x4a0090b0,
-	.cm_l4per_i2c4_clkctrl = 0x4a0090b8,
-	.cm_l4per_l4per_clkctrl = 0x4a0090c0,
-	.cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
-	.cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
-	.cm_l4per_mgate_clkctrl = 0x4a0090e8,
-	.cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
-	.cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
-	.cm_l4per_mcspi3_clkctrl = 0x4a009100,
-	.cm_l4per_mcspi4_clkctrl = 0x4a009108,
-	.cm_l4per_gpio7_clkctrl = 0x4a009110,
-	.cm_l4per_gpio8_clkctrl = 0x4a009118,
-	.cm_l4per_mmcsd3_clkctrl = 0x4a009120,
-	.cm_l4per_mmcsd4_clkctrl = 0x4a009128,
-	.cm_l4per_msprohg_clkctrl = 0x4a009130,
-	.cm_l4per_slimbus2_clkctrl = 0x4a009138,
-	.cm_l4per_uart1_clkctrl = 0x4a009140,
-	.cm_l4per_uart2_clkctrl = 0x4a009148,
-	.cm_l4per_uart3_clkctrl = 0x4a009150,
-	.cm_l4per_uart4_clkctrl = 0x4a009158,
-	.cm_l4per_mmcsd5_clkctrl = 0x4a009160,
-	.cm_l4per_i2c5_clkctrl = 0x4a009168,
-	.cm_l4per_uart5_clkctrl = 0x4a009170,
-	.cm_l4per_uart6_clkctrl = 0x4a009178,
-	.cm_l4sec_clkstctrl = 0x4a009180,
-	.cm_l4sec_staticdep = 0x4a009184,
-	.cm_l4sec_dynamicdep = 0x4a009188,
-	.cm_l4sec_aes1_clkctrl = 0x4a0091a0,
-	.cm_l4sec_aes2_clkctrl = 0x4a0091a8,
-	.cm_l4sec_des3des_clkctrl = 0x4a0091b0,
-	.cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
-	.cm_l4sec_rng_clkctrl = 0x4a0091c0,
-	.cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
-	.cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
-
-	/* cm2.ivahd */
-	.cm_ivahd_clkstctrl = 0x4a009200,
-	.cm_ivahd_ivahd_clkctrl = 0x4a009220,
-	.cm_ivahd_sl2_clkctrl = 0x4a009228,
-
-	/* cm2.cam */
-	.cm_cam_clkstctrl = 0x4a009300,
-	.cm_cam_iss_clkctrl = 0x4a009320,
-	.cm_cam_fdif_clkctrl = 0x4a009328,
-
-	/* cm2.dss */
-	.cm_dss_clkstctrl = 0x4a009400,
-	.cm_dss_dss_clkctrl = 0x4a009420,
-
-	/* cm2.sgx */
-	.cm_sgx_clkstctrl = 0x4a009500,
-	.cm_sgx_sgx_clkctrl = 0x4a009520,
-
-	/* cm2.l3init */
-	.cm_l3init_clkstctrl = 0x4a009600,
-
-	/* cm2.l3init */
-	.cm_l3init_hsmmc1_clkctrl = 0x4a009628,
-	.cm_l3init_hsmmc2_clkctrl = 0x4a009630,
-	.cm_l3init_hsi_clkctrl = 0x4a009638,
-	.cm_l3init_hsusbhost_clkctrl = 0x4a009658,
-	.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
-	.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
-	.cm_l3init_p1500_clkctrl = 0x4a009678,
-	.cm_l3init_sata_clkctrl = 0x4a009688,
-	.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
-	.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
-	.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
-	.cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0,
-
-	/* prm irqstatus regs */
-	.prm_irqstatus_mpu = 0x4ae06010,
-	.prm_irqstatus_mpu_2 = 0x4ae06014,
-
-	/* l4 wkup regs */
-	.cm_abe_pll_ref_clksel = 0x4ae0610c,
-	.cm_sys_clksel = 0x4ae06110,
-	.cm_wkup_clkstctrl = 0x4ae07900,
-	.cm_wkup_l4wkup_clkctrl = 0x4ae07920,
-	.cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
-	.cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
-	.cm_wkup_gpio1_clkctrl = 0x4ae07938,
-	.cm_wkup_gptimer1_clkctrl = 0x4ae07940,
-	.cm_wkup_gptimer12_clkctrl = 0x4ae07948,
-	.cm_wkup_synctimer_clkctrl = 0x4ae07950,
-	.cm_wkup_usim_clkctrl = 0x4ae07958,
-	.cm_wkup_sarram_clkctrl = 0x4ae07960,
-	.cm_wkup_keyboard_clkctrl = 0x4ae07978,
-	.cm_wkup_rtc_clkctrl = 0x4ae07980,
-	.cm_wkup_bandgap_clkctrl = 0x4ae07988,
-	.cm_wkupaon_scrm_clkctrl = 0x4ae07990,
-	.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
-	.prm_rstctrl = 0x4ae07c00,
-	.prm_rstst = 0x4ae07c04,
-	.prm_rsttime = 0x4ae07c08,
-	.prm_vc_val_bypass = 0x4ae07ca0,
-	.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
-	.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
-
-	.prm_abbldo_mpu_setup = 0x4ae07cdc,
-	.prm_abbldo_mpu_ctrl = 0x4ae07ce0,
-	.prm_abbldo_mm_setup = 0x4ae07ce4,
-	.prm_abbldo_mm_ctrl = 0x4ae07ce8,
-
-	/* SCRM stuff, used by some boards */
-	.scrm_auxclk0 = 0x4ae0a310,
-	.scrm_auxclk1 = 0x4ae0a314,
-};
-
-struct prcm_regs const dra7xx_prcm = {
-	/* cm1.ckgen */
-	.cm_clksel_core				= 0x4a005100,
-	.cm_clksel_abe				= 0x4a005108,
-	.cm_dll_ctrl				= 0x4a005110,
-	.cm_clkmode_dpll_core			= 0x4a005120,
-	.cm_idlest_dpll_core			= 0x4a005124,
-	.cm_autoidle_dpll_core			= 0x4a005128,
-	.cm_clksel_dpll_core			= 0x4a00512c,
-	.cm_div_m2_dpll_core			= 0x4a005130,
-	.cm_div_m3_dpll_core			= 0x4a005134,
-	.cm_div_h11_dpll_core			= 0x4a005138,
-	.cm_div_h12_dpll_core			= 0x4a00513c,
-	.cm_div_h13_dpll_core			= 0x4a005140,
-	.cm_div_h14_dpll_core			= 0x4a005144,
-	.cm_ssc_deltamstep_dpll_core		= 0x4a005148,
-	.cm_ssc_modfreqdiv_dpll_core		= 0x4a00514c,
-	.cm_div_h21_dpll_core			= 0x4a005150,
-	.cm_div_h22_dpllcore			= 0x4a005154,
-	.cm_div_h23_dpll_core			= 0x4a005158,
-	.cm_div_h24_dpll_core			= 0x4a00515c,
-	.cm_clkmode_dpll_mpu			= 0x4a005160,
-	.cm_idlest_dpll_mpu			= 0x4a005164,
-	.cm_autoidle_dpll_mpu			= 0x4a005168,
-	.cm_clksel_dpll_mpu			= 0x4a00516c,
-	.cm_div_m2_dpll_mpu			= 0x4a005170,
-	.cm_ssc_deltamstep_dpll_mpu		= 0x4a005188,
-	.cm_ssc_modfreqdiv_dpll_mpu		= 0x4a00518c,
-	.cm_bypclk_dpll_mpu			= 0x4a00519c,
-	.cm_clkmode_dpll_iva			= 0x4a0051a0,
-	.cm_idlest_dpll_iva			= 0x4a0051a4,
-	.cm_autoidle_dpll_iva			= 0x4a0051a8,
-	.cm_clksel_dpll_iva			= 0x4a0051ac,
-	.cm_ssc_deltamstep_dpll_iva		= 0x4a0051c8,
-	.cm_ssc_modfreqdiv_dpll_iva		= 0x4a0051cc,
-	.cm_bypclk_dpll_iva			= 0x4a0051dc,
-	.cm_clkmode_dpll_abe			= 0x4a0051e0,
-	.cm_idlest_dpll_abe			= 0x4a0051e4,
-	.cm_autoidle_dpll_abe			= 0x4a0051e8,
-	.cm_clksel_dpll_abe			= 0x4a0051ec,
-	.cm_div_m2_dpll_abe			= 0x4a0051f0,
-	.cm_div_m3_dpll_abe			= 0x4a0051f4,
-	.cm_ssc_deltamstep_dpll_abe		= 0x4a005208,
-	.cm_ssc_modfreqdiv_dpll_abe		= 0x4a00520c,
-	.cm_clkmode_dpll_ddrphy			= 0x4a005210,
-	.cm_idlest_dpll_ddrphy			= 0x4a005214,
-	.cm_autoidle_dpll_ddrphy		= 0x4a005218,
-	.cm_clksel_dpll_ddrphy			= 0x4a00521c,
-	.cm_div_m2_dpll_ddrphy			= 0x4a005220,
-	.cm_div_h11_dpll_ddrphy			= 0x4a005228,
-	.cm_ssc_deltamstep_dpll_ddrphy		= 0x4a00522c,
-	.cm_clkmode_dpll_dsp			= 0x4a005234,
-	.cm_shadow_freq_config1			= 0x4a005260,
-	.cm_clkmode_dpll_gmac			= 0x4a0052a8,
-	.cm_coreaon_usb_phy1_core_clkctrl	= 0x4a008640,
-	.cm_coreaon_usb_phy2_core_clkctrl	= 0x4a008688,
-	.cm_coreaon_usb_phy3_core_clkctrl	= 0x4a008698,
-	.cm_coreaon_l3init_60m_gfclk_clkctrl	= 0x4a0086c0,
-
-	/* cm1.mpu */
-	.cm_mpu_mpu_clkctrl			= 0x4a005320,
-
-	/* cm1.dsp */
-	.cm_dsp_clkstctrl			= 0x4a005400,
-	.cm_dsp_dsp_clkctrl			= 0x4a005420,
-
-	/* cm IPU */
-	.cm_ipu_clkstctrl			= 0x4a005540,
-	.cm_ipu_i2c5_clkctrl			= 0x4a005578,
-
-	/* prm irqstatus regs */
-	.prm_irqstatus_mpu			= 0x4ae06010,
-	.prm_irqstatus_mpu_2			= 0x4ae06014,
-
-	/* cm2.ckgen */
-	.cm_clksel_usb_60mhz			= 0x4a008104,
-	.cm_clkmode_dpll_per			= 0x4a008140,
-	.cm_idlest_dpll_per			= 0x4a008144,
-	.cm_autoidle_dpll_per			= 0x4a008148,
-	.cm_clksel_dpll_per			= 0x4a00814c,
-	.cm_div_m2_dpll_per			= 0x4a008150,
-	.cm_div_m3_dpll_per			= 0x4a008154,
-	.cm_div_h11_dpll_per			= 0x4a008158,
-	.cm_div_h12_dpll_per			= 0x4a00815c,
-	.cm_div_h13_dpll_per			= 0x4a008160,
-	.cm_div_h14_dpll_per			= 0x4a008164,
-	.cm_ssc_deltamstep_dpll_per		= 0x4a008168,
-	.cm_ssc_modfreqdiv_dpll_per		= 0x4a00816c,
-	.cm_clkmode_dpll_usb			= 0x4a008180,
-	.cm_idlest_dpll_usb			= 0x4a008184,
-	.cm_autoidle_dpll_usb			= 0x4a008188,
-	.cm_clksel_dpll_usb			= 0x4a00818c,
-	.cm_div_m2_dpll_usb			= 0x4a008190,
-	.cm_ssc_deltamstep_dpll_usb		= 0x4a0081a8,
-	.cm_ssc_modfreqdiv_dpll_usb		= 0x4a0081ac,
-	.cm_clkdcoldo_dpll_usb			= 0x4a0081b4,
-	.cm_clkmode_dpll_pcie_ref		= 0x4a008200,
-	.cm_clkmode_apll_pcie			= 0x4a00821c,
-	.cm_idlest_apll_pcie			= 0x4a008220,
-	.cm_div_m2_apll_pcie			= 0x4a008224,
-	.cm_clkvcoldo_apll_pcie			= 0x4a008228,
-
-	/* cm2.core */
-	.cm_l3_1_clkstctrl			= 0x4a008700,
-	.cm_l3_1_dynamicdep			= 0x4a008708,
-	.cm_l3_1_l3_1_clkctrl			= 0x4a008720,
-	.cm_l3_gpmc_clkctrl			= 0x4a008728,
-	.cm_mpu_m3_clkstctrl			= 0x4a008900,
-	.cm_mpu_m3_staticdep			= 0x4a008904,
-	.cm_mpu_m3_dynamicdep			= 0x4a008908,
-	.cm_mpu_m3_mpu_m3_clkctrl		= 0x4a008920,
-	.cm_sdma_clkstctrl			= 0x4a008a00,
-	.cm_sdma_staticdep			= 0x4a008a04,
-	.cm_sdma_dynamicdep			= 0x4a008a08,
-	.cm_sdma_sdma_clkctrl			= 0x4a008a20,
-	.cm_memif_clkstctrl			= 0x4a008b00,
-	.cm_memif_dmm_clkctrl			= 0x4a008b20,
-	.cm_memif_emif_fw_clkctrl		= 0x4a008b28,
-	.cm_memif_emif_1_clkctrl		= 0x4a008b30,
-	.cm_memif_emif_2_clkctrl		= 0x4a008b38,
-	.cm_memif_dll_clkctrl			= 0x4a008b40,
-	.cm_l4cfg_clkstctrl			= 0x4a008d00,
-	.cm_l4cfg_dynamicdep			= 0x4a008d08,
-	.cm_l4cfg_l4_cfg_clkctrl		= 0x4a008d20,
-	.cm_l4cfg_hw_sem_clkctrl		= 0x4a008d28,
-	.cm_l4cfg_mailbox_clkctrl		= 0x4a008d30,
-	.cm_l4cfg_sar_rom_clkctrl		= 0x4a008d38,
-	.cm_l3instr_clkstctrl			= 0x4a008e00,
-	.cm_l3instr_l3_3_clkctrl		= 0x4a008e20,
-	.cm_l3instr_l3_instr_clkctrl		= 0x4a008e28,
-	.cm_l3instr_intrconn_wp1_clkctrl	= 0x4a008e40,
-
-	/* cm2.ivahd */
-	.cm_ivahd_clkstctrl			= 0x4a008f00,
-	.cm_ivahd_ivahd_clkctrl			= 0x4a008f20,
-	.cm_ivahd_sl2_clkctrl			= 0x4a008f28,
-
-	/* cm2.cam */
-	.cm_cam_clkstctrl			= 0x4a009000,
-	.cm_cam_vip1_clkctrl			= 0x4a009020,
-	.cm_cam_vip2_clkctrl			= 0x4a009028,
-	.cm_cam_vip3_clkctrl			= 0x4a009030,
-	.cm_cam_lvdsrx_clkctrl			= 0x4a009038,
-	.cm_cam_csi1_clkctrl			= 0x4a009040,
-	.cm_cam_csi2_clkctrl			= 0x4a009048,
-
-	/* cm2.dss */
-	.cm_dss_clkstctrl			= 0x4a009100,
-	.cm_dss_dss_clkctrl			= 0x4a009120,
-
-	/* cm2.sgx */
-	.cm_sgx_clkstctrl			= 0x4a009200,
-	.cm_sgx_sgx_clkctrl			= 0x4a009220,
-
-	/* cm2.l3init */
-	.cm_l3init_clkstctrl			= 0x4a009300,
-
-	/* cm2.l3init */
-	.cm_l3init_hsmmc1_clkctrl		= 0x4a009328,
-	.cm_l3init_hsmmc2_clkctrl		= 0x4a009330,
-	.cm_l3init_hsusbhost_clkctrl		= 0x4a009340,
-	.cm_l3init_hsusbotg_clkctrl		= 0x4a009348,
-	.cm_l3init_hsusbtll_clkctrl		= 0x4a009350,
-	.cm_l3init_sata_clkctrl			= 0x4a009388,
-	.cm_gmac_clkstctrl			= 0x4a0093c0,
-	.cm_gmac_gmac_clkctrl			= 0x4a0093d0,
-	.cm_l3init_ocp2scp1_clkctrl		= 0x4a0093e0,
-	.cm_l3init_ocp2scp3_clkctrl		= 0x4a0093e8,
-	.cm_l3init_usb_otg_ss1_clkctrl		= 0x4a0093f0,
-	.cm_l3init_usb_otg_ss2_clkctrl		= 0x4a009340,
-
-	/* cm2.l4per */
-	.cm_l4per_clkstctrl			= 0x4a009700,
-	.cm_l4per_dynamicdep			= 0x4a009708,
-	.cm_l4per_gptimer10_clkctrl		= 0x4a009728,
-	.cm_l4per_gptimer11_clkctrl		= 0x4a009730,
-	.cm_l4per_gptimer2_clkctrl		= 0x4a009738,
-	.cm_l4per_gptimer3_clkctrl		= 0x4a009740,
-	.cm_l4per_gptimer4_clkctrl		= 0x4a009748,
-	.cm_l4per_gptimer9_clkctrl		= 0x4a009750,
-	.cm_l4per_elm_clkctrl			= 0x4a009758,
-	.cm_l4per_gpio2_clkctrl			= 0x4a009760,
-	.cm_l4per_gpio3_clkctrl			= 0x4a009768,
-	.cm_l4per_gpio4_clkctrl			= 0x4a009770,
-	.cm_l4per_gpio5_clkctrl			= 0x4a009778,
-	.cm_l4per_gpio6_clkctrl			= 0x4a009780,
-	.cm_l4per_hdq1w_clkctrl			= 0x4a009788,
-	.cm_l4per_i2c1_clkctrl			= 0x4a0097a0,
-	.cm_l4per_i2c2_clkctrl			= 0x4a0097a8,
-	.cm_l4per_i2c3_clkctrl			= 0x4a0097b0,
-	.cm_l4per_i2c4_clkctrl			= 0x4a0097b8,
-	.cm_l4per_l4per_clkctrl			= 0x4a0097c0,
-	.cm_l4per_mcspi1_clkctrl		= 0x4a0097f0,
-	.cm_l4per_mcspi2_clkctrl		= 0x4a0097f8,
-	.cm_l4per_mcspi3_clkctrl		= 0x4a009800,
-	.cm_l4per_mcspi4_clkctrl		= 0x4a009808,
-	.cm_l4per_gpio7_clkctrl			= 0x4a009810,
-	.cm_l4per_gpio8_clkctrl			= 0x4a009818,
-	.cm_l4per_mmcsd3_clkctrl		= 0x4a009820,
-	.cm_l4per_mmcsd4_clkctrl		= 0x4a009828,
-	.cm_l4per_qspi_clkctrl			= 0x4a009838,
-	.cm_l4per_uart1_clkctrl			= 0x4a009840,
-	.cm_l4per_uart2_clkctrl			= 0x4a009848,
-	.cm_l4per_uart3_clkctrl			= 0x4a009850,
-	.cm_l4per_uart4_clkctrl			= 0x4a009858,
-	.cm_l4per_uart5_clkctrl			= 0x4a009870,
-	.cm_l4sec_clkstctrl			= 0x4a009880,
-	.cm_l4sec_staticdep			= 0x4a009884,
-	.cm_l4sec_dynamicdep			= 0x4a009888,
-	.cm_l4sec_aes1_clkctrl			= 0x4a0098a0,
-	.cm_l4sec_aes2_clkctrl			= 0x4a0098a8,
-	.cm_l4sec_des3des_clkctrl		= 0x4a0098b0,
-	.cm_l4sec_rng_clkctrl			= 0x4a0098c0,
-	.cm_l4sec_sha2md51_clkctrl		= 0x4a0098c8,
-	.cm_l4sec_cryptodma_clkctrl		= 0x4a0098d8,
-
-	/* l4 wkup regs */
-	.cm_abe_pll_ref_clksel			= 0x4ae0610c,
-	.cm_sys_clksel				= 0x4ae06110,
-	.cm_abe_pll_sys_clksel			= 0x4ae06118,
-	.cm_wkup_clkstctrl			= 0x4ae07800,
-	.cm_wkup_l4wkup_clkctrl			= 0x4ae07820,
-	.cm_wkup_wdtimer1_clkctrl		= 0x4ae07828,
-	.cm_wkup_wdtimer2_clkctrl		= 0x4ae07830,
-	.cm_wkup_gpio1_clkctrl			= 0x4ae07838,
-	.cm_wkup_gptimer1_clkctrl		= 0x4ae07840,
-	.cm_wkup_gptimer12_clkctrl		= 0x4ae07848,
-	.cm_wkup_sarram_clkctrl			= 0x4ae07860,
-	.cm_wkup_keyboard_clkctrl		= 0x4ae07878,
-	.cm_wkupaon_scrm_clkctrl		= 0x4ae07890,
-	.prm_rstctrl				= 0x4ae07d00,
-	.prm_rstst				= 0x4ae07d04,
-	.prm_rsttime				= 0x4ae07d08,
-	.prm_io_pmctrl				= 0x4ae07d20,
-	.prm_vc_val_bypass			= 0x4ae07da0,
-	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
-	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,
-
-	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
-	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
-	.prm_abbldo_iva_setup			= 0x4AE07E34,
-	.prm_abbldo_iva_ctrl			= 0x4AE07E24,
-	.prm_abbldo_eve_setup			= 0x4AE07E30,
-	.prm_abbldo_eve_ctrl			= 0x4AE07E20,
-	.prm_abbldo_gpu_setup			= 0x4AE07DE4,
-	.prm_abbldo_gpu_ctrl			= 0x4AE07DE8,
-
-	/*l3main1 edma*/
-	.cm_l3main1_tptc1_clkctrl               = 0x4a008778,
-	.cm_l3main1_tptc2_clkctrl               = 0x4a008780,
-};
-
-void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits)
-{
-	u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 :
-		(*ctrl)->ctrl_core_sma_sw_0;
-	clrsetbits_le32(reg, clear_bits, set_bits);
-}
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
deleted file mode 100644
index 7712923..0000000
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ /dev/null
@@ -1,742 +0,0 @@
-/*
- * Timing and Organization details of the ddr device parts used in OMAP5
- * EVM
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/emif.h>
-#include <asm/arch/sys_proto.h>
-
-/*
- * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
- * EVM. Since the parts used and geometry are identical for
- * evm for a given OMAP5 revision, this information is kept
- * here instead of being in board directory. However the key functions
- * exported are weakly linked so that they can be over-ridden in the board
- * directory if there is a OMAP5 board in the future that uses a different
- * memory device or geometry.
- *
- * For any new board with different memory devices over-ride one or more
- * of the following functions as per the CONFIG flags you intend to enable:
- * - emif_get_reg_dump()
- * - emif_get_dmm_regs()
- * - emif_get_device_details()
- * - emif_get_device_timings()
- */
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-const struct emif_regs emif_regs_532_mhz_2cs = {
-	.sdram_config_init		= 0x80800EBA,
-	.sdram_config			= 0x808022BA,
-	.ref_ctrl			= 0x0000081A,
-	.sdram_tim1			= 0x772F6873,
-	.sdram_tim2			= 0x304a129a,
-	.sdram_tim3			= 0x02f7e45f,
-	.read_idle_ctrl			= 0x00050000,
-	.zq_config			= 0x000b3215,
-	.temp_alert_config		= 0x08000a05,
-	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
-	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
-	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
-	.emif_ddr_ext_phy_ctrl_2	= 0x28C518A3,
-	.emif_ddr_ext_phy_ctrl_3	= 0x518A3146,
-	.emif_ddr_ext_phy_ctrl_4	= 0x0014628C,
-	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
-};
-
-const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
-	.sdram_config_init		= 0x80800EBA,
-	.sdram_config			= 0x808022BA,
-	.ref_ctrl			= 0x0000081A,
-	.sdram_tim1			= 0x772F6873,
-	.sdram_tim2			= 0x304a129a,
-	.sdram_tim3			= 0x02f7e45f,
-	.read_idle_ctrl			= 0x00050000,
-	.zq_config			= 0x100b3215,
-	.temp_alert_config		= 0x08000a05,
-	.emif_ddr_phy_ctlr_1_init	= 0x0E30400d,
-	.emif_ddr_phy_ctlr_1		= 0x0E30400d,
-	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
-	.emif_ddr_ext_phy_ctrl_2	= 0x28C518A3,
-	.emif_ddr_ext_phy_ctrl_3	= 0x518A3146,
-	.emif_ddr_ext_phy_ctrl_4	= 0x0014628C,
-	.emif_ddr_ext_phy_ctrl_5	= 0xC330CC33,
-};
-
-const struct emif_regs emif_regs_266_mhz_2cs = {
-	.sdram_config_init		= 0x80800EBA,
-	.sdram_config			= 0x808022BA,
-	.ref_ctrl			= 0x0000040D,
-	.sdram_tim1			= 0x2A86B419,
-	.sdram_tim2			= 0x1025094A,
-	.sdram_tim3			= 0x026BA22F,
-	.read_idle_ctrl			= 0x00050000,
-	.zq_config			= 0x000b3215,
-	.temp_alert_config		= 0x08000a05,
-	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
-	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
-	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
-	.emif_ddr_ext_phy_ctrl_2	= 0x0A414829,
-	.emif_ddr_ext_phy_ctrl_3	= 0x14829052,
-	.emif_ddr_ext_phy_ctrl_4	= 0x000520A4,
-	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
-};
-
-const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
-	.sdram_config_init		= 0x61851B32,
-	.sdram_config			= 0x61851B32,
-	.sdram_config2			= 0x0,
-	.ref_ctrl			= 0x00001035,
-	.sdram_tim1			= 0xCCCF36B3,
-	.sdram_tim2			= 0x308F7FDA,
-	.sdram_tim3			= 0x027F88A8,
-	.read_idle_ctrl			= 0x00050000,
-	.zq_config			= 0x0007190B,
-	.temp_alert_config		= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init	= 0x0020420A,
-	.emif_ddr_phy_ctlr_1		= 0x0024420A,
-	.emif_ddr_ext_phy_ctrl_1	= 0x04040100,
-	.emif_ddr_ext_phy_ctrl_2	= 0x00000000,
-	.emif_ddr_ext_phy_ctrl_3	= 0x00000000,
-	.emif_ddr_ext_phy_ctrl_4	= 0x00000000,
-	.emif_ddr_ext_phy_ctrl_5	= 0x04010040,
-	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
-	.emif_rd_wr_lvl_ctl		= 0x00000000,
-	.emif_rd_wr_exec_thresh		= 0x00000305
-};
-
-const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
-	.sdram_config_init              = 0x61851B32,
-	.sdram_config                   = 0x61851B32,
-	.sdram_config2			= 0x0,
-	.ref_ctrl                       = 0x00001035,
-	.sdram_tim1                     = 0xCCCF36B3,
-	.sdram_tim2                     = 0x308F7FDA,
-	.sdram_tim3                     = 0x027F88A8,
-	.read_idle_ctrl                 = 0x00050000,
-	.zq_config                      = 0x1007190B,
-	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0030400A,
-	.emif_ddr_phy_ctlr_1            = 0x0034400A,
-	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
-	.emif_ddr_ext_phy_ctrl_2        = 0x00000000,
-	.emif_ddr_ext_phy_ctrl_3        = 0x00000000,
-	.emif_ddr_ext_phy_ctrl_4        = 0x00000000,
-	.emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
-	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
-	.emif_rd_wr_lvl_ctl             = 0x00000000,
-	.emif_rd_wr_exec_thresh         = 0x40000305
-};
-
-const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
-	.dmm_lisa_map_0 = 0x0,
-	.dmm_lisa_map_1 = 0x0,
-	.dmm_lisa_map_2 = 0x80740300,
-	.dmm_lisa_map_3 = 0xFF020100,
-	.is_ma_present	= 0x1
-};
-
-static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
-{
-	switch (omap_revision()) {
-	case OMAP5430_ES1_0:
-		*regs = &emif_regs_532_mhz_2cs;
-		break;
-	case OMAP5432_ES1_0:
-		*regs = &emif_regs_ddr3_532_mhz_1cs;
-		break;
-	case OMAP5430_ES2_0:
-		*regs = &emif_regs_532_mhz_2cs_es2;
-		break;
-	case OMAP5432_ES2_0:
-	default:
-		*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
-		break;
-	}
-}
-
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
-	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
-
-static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
-						**dmm_lisa_regs)
-{
-	switch (omap_revision()) {
-	case OMAP5430_ES1_0:
-	case OMAP5430_ES2_0:
-	case OMAP5432_ES1_0:
-	case OMAP5432_ES2_0:
-	default:
-		*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
-		break;
-	}
-
-}
-
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
-	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
-#else
-
-static const struct lpddr2_device_details dev_4G_S4_details = {
-	.type		= LPDDR2_TYPE_S4,
-	.density	= LPDDR2_DENSITY_4Gb,
-	.io_width	= LPDDR2_IO_WIDTH_32,
-	.manufacturer	= LPDDR2_MANUFACTURER_SAMSUNG
-};
-
-static void emif_get_device_details_sdp(u32 emif_nr,
-		struct lpddr2_device_details *cs0_device_details,
-		struct lpddr2_device_details *cs1_device_details)
-{
-	/* EMIF1 & EMIF2 have identical configuration */
-	*cs0_device_details = dev_4G_S4_details;
-	*cs1_device_details = dev_4G_S4_details;
-}
-
-void emif_get_device_details(u32 emif_nr,
-		struct lpddr2_device_details *cs0_device_details,
-		struct lpddr2_device_details *cs1_device_details)
-	__attribute__((weak, alias("emif_get_device_details_sdp")));
-
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
-const u32 ext_phy_ctrl_const_base[] = {
-	0x01004010,
-	0x00001004,
-	0x04010040,
-	0x01004010,
-	0x00001004,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x80080080,
-	0x00800800,
-	0x08102040,
-	0x00000001,
-	0x540A8150,
-	0xA81502a0,
-	0x002A0540,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000077,
-	0x0
-};
-
-const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
-	0x01004010,
-	0x00001004,
-	0x04010040,
-	0x01004010,
-	0x00001004,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x80080080,
-	0x00800800,
-	0x08102040,
-	0x00000002,
-	0x0,
-	0x0,
-	0x0,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000057,
-	0x0
-};
-
-const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
-	0x50D4350D,
-	0x00000D43,
-	0x04010040,
-	0x01004010,
-	0x00001004,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x80080080,
-	0x00800800,
-	0x08102040,
-	0x00000002,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000057,
-	0x0
-};
-
-/* Ext phy ctrl 1-35 regs */
-const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
-	0x10040100,
-	0x00910091,
-	0x00950095,
-	0x009B009B,
-	0x009E009E,
-	0x00980098,
-	0x00340034,
-	0x00350035,
-	0x00340034,
-	0x00310031,
-	0x00340034,
-	0x007F007F,
-	0x007F007F,
-	0x007F007F,
-	0x007F007F,
-	0x007F007F,
-	0x00480048,
-	0x004A004A,
-	0x00520052,
-	0x00550055,
-	0x00500050,
-	0x00000000,
-	0x00600020,
-	0x40011080,
-	0x08102040,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0
-};
-
-/* Ext phy ctrl 1-35 regs */
-const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
-	0x10040100,
-	0x00910091,
-	0x00950095,
-	0x009B009B,
-	0x009E009E,
-	0x00980098,
-	0x00330033,
-	0x00330033,
-	0x002F002F,
-	0x00320032,
-	0x00310031,
-	0x007F007F,
-	0x007F007F,
-	0x007F007F,
-	0x007F007F,
-	0x007F007F,
-	0x00520052,
-	0x00520052,
-	0x00470047,
-	0x00490049,
-	0x00500050,
-	0x00000000,
-	0x00600020,
-	0x40011080,
-	0x08102040,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0
-};
-
-/* Ext phy ctrl 1-35 regs */
-const u32
-dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
-	0x10040100,
-	0x00A400A4,
-	0x00A900A9,
-	0x00B000B0,
-	0x00B000B0,
-	0x00A400A4,
-	0x00390039,
-	0x00320032,
-	0x00320032,
-	0x00320032,
-	0x00440044,
-	0x00550055,
-	0x00550055,
-	0x00550055,
-	0x00550055,
-	0x007F007F,
-	0x004D004D,
-	0x00430043,
-	0x00560056,
-	0x00540054,
-	0x00600060,
-	0x0,
-	0x00600020,
-	0x40010080,
-	0x08102040,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0,
-	0x0
-};
-
-const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
-	0x04040100,
-	0x006B009F,
-	0x006B00A2,
-	0x006B00A8,
-	0x006B00A8,
-	0x006B00B2,
-	0x002F002F,
-	0x002F002F,
-	0x002F002F,
-	0x002F002F,
-	0x002F002F,
-	0x00600073,
-	0x00600071,
-	0x0060007C,
-	0x0060007E,
-	0x00600084,
-	0x00400053,
-	0x00400051,
-	0x0040005C,
-	0x0040005E,
-	0x00400064,
-	0x00800080,
-	0x00800080,
-	0x40010080,
-	0x08102040,
-	0x005B008F,
-	0x005B0092,
-	0x005B0098,
-	0x005B0098,
-	0x005B00A2,
-	0x00300043,
-	0x00300041,
-	0x0030004C,
-	0x0030004E,
-	0x00300054,
-	0x00000077
-};
-
-const struct lpddr2_mr_regs mr_regs = {
-	.mr1	= MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
-	.mr2	= 0x6,
-	.mr3	= 0x1,
-	.mr10	= MR10_ZQ_ZQINIT,
-	.mr16	= MR16_REF_FULL_ARRAY
-};
-
-void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
-					     const u32 **regs,
-					     u32 *size)
-{
-	switch (omap_revision()) {
-	case OMAP5430_ES1_0:
-	case OMAP5430_ES2_0:
-		*regs = ext_phy_ctrl_const_base;
-		*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
-		break;
-	case OMAP5432_ES1_0:
-		*regs = ddr3_ext_phy_ctrl_const_base_es1;
-		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
-		break;
-	case OMAP5432_ES2_0:
-		*regs = ddr3_ext_phy_ctrl_const_base_es2;
-		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
-		break;
-	case DRA752_ES1_0:
-	case DRA752_ES1_1:
-	case DRA752_ES2_0:
-		if (emif_nr == 1) {
-			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
-			*size =
-			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
-		} else {
-			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
-			*size =
-			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
-		}
-		break;
-	case DRA722_ES1_0:
-		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
-		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
-		break;
-	case DRA722_ES2_0:
-		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
-		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
-		break;
-	default:
-		*regs = ddr3_ext_phy_ctrl_const_base_es2;
-		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
-
-	}
-}
-
-void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
-{
-	*regs = &mr_regs;
-}
-
-static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
-{
-	u32 *ext_phy_ctrl_base = 0;
-	u32 *emif_ext_phy_ctrl_base = 0;
-	u32 emif_nr;
-	const u32 *ext_phy_ctrl_const_regs;
-	u32 i = 0;
-	u32 size;
-
-	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
-
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
-	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
-	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
-	/* Configure external phy control timing registers */
-	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
-		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
-		/* Update shadow registers */
-		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
-	}
-
-	/*
-	 * external phy 6-24 registers do not change with
-	 * ddr frequency
-	 */
-	emif_get_ext_phy_ctrl_const_regs(emif_nr,
-					 &ext_phy_ctrl_const_regs, &size);
-
-	for (i = 0; i < size; i++) {
-		writel(ext_phy_ctrl_const_regs[i],
-		       emif_ext_phy_ctrl_base++);
-		/* Update shadow registers */
-		writel(ext_phy_ctrl_const_regs[i],
-		       emif_ext_phy_ctrl_base++);
-	}
-}
-
-static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
-{
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-	u32 *emif_ext_phy_ctrl_base = 0;
-	u32 emif_nr;
-	const u32 *ext_phy_ctrl_const_regs;
-	u32 i, hw_leveling, size, phy;
-
-	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
-
-	hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
-	phy = regs->emif_ddr_phy_ctlr_1_init;
-
-	emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
-
-	emif_get_ext_phy_ctrl_const_regs(emif_nr,
-					 &ext_phy_ctrl_const_regs, &size);
-
-	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
-	writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
-
-	/*
-	 * Copy the predefined PHY register values
-	 * if leveling is disabled.
-	 */
-	if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
-		for (i = 1; i < 6; i++) {
-			writel(ext_phy_ctrl_const_regs[i],
-			       &emif_ext_phy_ctrl_base[i * 2]);
-			writel(ext_phy_ctrl_const_regs[i],
-			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
-		}
-
-	if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
-		for (i = 6; i < 11; i++) {
-			writel(ext_phy_ctrl_const_regs[i],
-			       &emif_ext_phy_ctrl_base[i * 2]);
-			writel(ext_phy_ctrl_const_regs[i],
-			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
-		}
-
-	if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
-		for (i = 11; i < 25; i++) {
-			writel(ext_phy_ctrl_const_regs[i],
-			       &emif_ext_phy_ctrl_base[i * 2]);
-			writel(ext_phy_ctrl_const_regs[i],
-			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
-		}
-
-	if (hw_leveling) {
-		/*
-		 * Write the init value for HW levling to occur
-		 */
-		for (i = 21; i < 35; i++) {
-			writel(ext_phy_ctrl_const_regs[i],
-			       &emif_ext_phy_ctrl_base[i * 2]);
-			writel(ext_phy_ctrl_const_regs[i],
-			       &emif_ext_phy_ctrl_base[i * 2 + 1]);
-		}
-	}
-}
-
-void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
-{
-	if (is_omap54xx())
-		do_ext_phy_settings_omap5(base, regs);
-	else
-		do_ext_phy_settings_dra7(base, regs);
-}
-
-#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
-	.max_freq	= 532000000,
-	.RL		= 8,
-	.tRPab		= 21,
-	.tRCD		= 18,
-	.tWR		= 15,
-	.tRASmin	= 42,
-	.tRRD		= 10,
-	.tWTRx2		= 15,
-	.tXSR		= 140,
-	.tXPx2		= 15,
-	.tRFCab		= 130,
-	.tRTPx2		= 15,
-	.tCKE		= 3,
-	.tCKESR		= 15,
-	.tZQCS		= 90,
-	.tZQCL		= 360,
-	.tZQINIT	= 1000,
-	.tDQSCKMAXx2	= 11,
-	.tRASmax	= 70,
-	.tFAW		= 50
-};
-
-static const struct lpddr2_min_tck min_tck = {
-	.tRL		= 3,
-	.tRP_AB		= 3,
-	.tRCD		= 3,
-	.tWR		= 3,
-	.tRAS_MIN	= 3,
-	.tRRD		= 2,
-	.tWTR		= 2,
-	.tXP		= 2,
-	.tRTP		= 2,
-	.tCKE		= 3,
-	.tCKESR		= 3,
-	.tFAW		= 8
-};
-
-static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
-	&timings_jedec_532_mhz
-};
-
-static const struct lpddr2_device_timings dev_4G_S4_timings = {
-	.ac_timings	= ac_timings,
-	.min_tck	= &min_tck,
-};
-
-/*
- * List of status registers to be controlled back to control registers
- * after initial leveling
- * readreg, writereg
- */
-const struct read_write_regs omap5_bug_00339_regs[] = {
-	{ 8,  5 },
-	{ 9,  6 },
-	{ 10, 7 },
-	{ 14, 8 },
-	{ 15, 9 },
-	{ 16, 10 },
-	{ 11, 2 },
-	{ 12, 3 },
-	{ 13, 4 },
-	{ 17, 11 },
-	{ 18, 12 },
-	{ 19, 13 },
-};
-
-const struct read_write_regs dra_bug_00339_regs[] = {
-	{ 7,  7 },
-	{ 8,  8 },
-	{ 9,  9 },
-	{ 10, 10 },
-	{ 11, 11 },
-	{ 12, 2 },
-	{ 13, 3 },
-	{ 14, 4 },
-	{ 15, 5 },
-	{ 16, 6 },
-	{ 17, 12 },
-	{ 18, 13 },
-	{ 19, 14 },
-	{ 20, 15 },
-	{ 21, 16 },
-	{ 22, 17 },
-	{ 23, 18 },
-	{ 24, 19 },
-	{ 25, 20 },
-	{ 26, 21}
-};
-
-const struct read_write_regs *get_bug_regs(u32 *iterations)
-{
-	const struct read_write_regs *bug_00339_regs_ptr = NULL;
-
-	switch (omap_revision()) {
-	case OMAP5430_ES1_0:
-	case OMAP5430_ES2_0:
-	case OMAP5432_ES1_0:
-	case OMAP5432_ES2_0:
-		bug_00339_regs_ptr = omap5_bug_00339_regs;
-		*iterations = sizeof(omap5_bug_00339_regs)/
-			     sizeof(omap5_bug_00339_regs[0]);
-		break;
-	case DRA752_ES1_0:
-	case DRA752_ES1_1:
-	case DRA752_ES2_0:
-	case DRA722_ES1_0:
-	case DRA722_ES2_0:
-		bug_00339_regs_ptr = dra_bug_00339_regs;
-		*iterations = sizeof(dra_bug_00339_regs)/
-			     sizeof(dra_bug_00339_regs[0]);
-		break;
-	default:
-		printf("\n Error: UnKnown SOC");
-	}
-
-	return bug_00339_regs_ptr;
-}
-
-void emif_get_device_timings_sdp(u32 emif_nr,
-		const struct lpddr2_device_timings **cs0_device_timings,
-		const struct lpddr2_device_timings **cs1_device_timings)
-{
-	/* Identical devices on EMIF1 & EMIF2 */
-	*cs0_device_timings = &dev_4G_S4_timings;
-	*cs1_device_timings = &dev_4G_S4_timings;
-}
-
-void emif_get_device_timings(u32 emif_nr,
-		const struct lpddr2_device_timings **cs0_device_timings,
-		const struct lpddr2_device_timings **cs1_device_timings)
-	__attribute__((weak, alias("emif_get_device_timings_sdp")));
-
-#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
diff --git a/arch/arm/cpu/armv7/omap5/sec-fxns.c b/arch/arm/cpu/armv7/omap5/sec-fxns.c
deleted file mode 100644
index 33d4ea4..0000000
--- a/arch/arm/cpu/armv7/omap5/sec-fxns.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *
- * Security related functions for OMAP5 class devices
- *
- * (C) Copyright 2016
- * Texas Instruments, <www.ti.com>
- *
- * Daniel Allred <d-allred@ti.com>
- * Harinarayan Bhatta <harinarayan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stdarg.h>
-
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_common.h>
-#include <asm/omap_sec_common.h>
-#include <asm/spl.h>
-#include <spl.h>
-
-/* Index for signature PPA-based TI HAL APIs */
-#define PPA_HAL_SERVICES_START_INDEX        (0x200)
-#define PPA_SERV_HAL_SETUP_SEC_RESVD_REGION (PPA_HAL_SERVICES_START_INDEX + 25)
-#define PPA_SERV_HAL_SETUP_EMIF_FW_REGION   (PPA_HAL_SERVICES_START_INDEX + 26)
-#define PPA_SERV_HAL_LOCK_EMIF_FW           (PPA_HAL_SERVICES_START_INDEX + 27)
-
-static u32 get_sec_mem_start(void)
-{
-	u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
-	u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
-	/*
-	 * Total reserved region is all contiguous with protected
-	 * region coming first, followed by the non-secure region.
-	 * If 0x0 start address is given, we simply put the reserved
-	 * region at the end of the external DRAM.
-	 */
-	if (sec_mem_start == 0)
-		sec_mem_start =
-			(CONFIG_SYS_SDRAM_BASE +
-			(omap_sdram_size() - sec_mem_size));
-	return sec_mem_start;
-}
-
-int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr,
-			       uint32_t size, uint32_t access_perm,
-			       uint32_t initiator_perm)
-{
-	int result = 1;
-
-	/*
-	 * Call PPA HAL API to do any other general firewall
-	 * configuration for regions 1-6 of the EMIF firewall.
-	 */
-	debug("%s: regionNum = %x, startAddr = %x, size = %x", __func__,
-	      region_num, start_addr, size);
-
-	result = secure_rom_call(
-			PPA_SERV_HAL_SETUP_EMIF_FW_REGION, 0, 0, 4,
-			(start_addr & 0xFFFFFFF0) | (region_num & 0x0F),
-			size, access_perm, initiator_perm);
-
-	if (result != 0) {
-		puts("Secure EMIF Firewall Setup failed!\n");
-		debug("Return Value = %x\n", result);
-	}
-
-	return result;
-}
-
-#if	(CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE <  \
-	CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE)
-#error	"TI Secure EMIF: Protected size cannot be larger than total size."
-#endif
-int secure_emif_reserve(void)
-{
-	int result = 1;
-	u32 sec_mem_start = get_sec_mem_start();
-	u32 sec_prot_size = CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE;
-
-	/* If there is no protected region, there is no reservation to make */
-	if (sec_prot_size == 0)
-		return 0;
-
-	/*
-	 * Call PPA HAL API to reserve a chunk of EMIF SDRAM
-	 * for secure world use. This region should be carved out
-	 * from use by any public code. EMIF firewall region 7
-	 * will be used to protect this block of memory.
-	 */
-	result = secure_rom_call(
-			PPA_SERV_HAL_SETUP_SEC_RESVD_REGION,
-			0, 0, 2, sec_mem_start, sec_prot_size);
-
-	if (result != 0) {
-		puts("SDRAM Firewall: Secure memory reservation failed!\n");
-		debug("Return Value = %x\n", result);
-	}
-
-	return result;
-}
-
-int secure_emif_firewall_lock(void)
-{
-	int result = 1;
-
-	/*
-	 * Call PPA HAL API to lock the EMIF firewall configurations.
-	 * After this API is called, none of the PPA HAL APIs for
-	 * configuring the EMIF firewalls will be usable again (that
-	 * is, calls to those APIs will return failure and have no
-	 * effect).
-	 */
-
-	result = secure_rom_call(
-			PPA_SERV_HAL_LOCK_EMIF_FW,
-			0, 0, 0);
-
-	if (result != 0) {
-		puts("Secure EMIF Firewall Lock failed!\n");
-		debug("Return Value = %x\n", result);
-	}
-
-	return result;
-}