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| author | Hans de Goede <hdegoede@redhat.com> | 2014-12-27 16:56:59 (GMT) |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-01-14 13:56:37 (GMT) |
| commit | 25508ab26cb9ceb8ac9cdf12a851b7047fa791b2 (patch) | |
| tree | c472b895a16a2ca13c3a625cd83bbf4ac8013019 /arch/arm/cpu/armv7/sunxi/clock_sun6i.c | |
| parent | c3d2b963c6a0b85a60c918b970db59c5b210fc98 (diff) | |
| download | u-boot-25508ab26cb9ceb8ac9cdf12a851b7047fa791b2.tar.xz | |
sunxi: Fix PLL1 running at half speed on sun8i
PLL1 on sun6i / sun8i also has a p factor which divides the clock by
2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is
used and we were setting it to 1, resulting in the CPU running at 504 MHz
instead of 1008 MHz, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/cpu/armv7/sunxi/clock_sun6i.c')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index ad50dd9..d7a7040 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -97,6 +97,7 @@ void clock_set_pll1(unsigned int clk) { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; int k = 1; int m = 1; @@ -113,8 +114,11 @@ void clock_set_pll1(unsigned int clk) CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, &ccm->cpu_axi_cfg); - /* PLL1 rate = 24000000 * n * k / m */ - writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC | + /* + * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored) + * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m + */ + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); sdelay(200); |