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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-04-21 19:01:35 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-04-21 19:01:35 (GMT) |
| commit | c9aab0f9dd23fddcebf5984dc19e62b514e759a7 (patch) | |
| tree | 65ce91815907466f07e87d8b79eaf19763c282bf /arch/arm/cpu/armv7/syslib.c | |
| parent | 94b972d366c29b92319865e3ded16da062aa8507 (diff) | |
| parent | 2e8f5dc16ad360cc15ea402a1dc4d421a04adbbd (diff) | |
| download | u-boot-c9aab0f9dd23fddcebf5984dc19e62b514e759a7.tar.xz | |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/cpu/armv7/syslib.c')
| -rw-r--r-- | arch/arm/cpu/armv7/syslib.c | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c index caf9fbc..4ae2596 100644 --- a/arch/arm/cpu/armv7/syslib.c +++ b/arch/arm/cpu/armv7/syslib.c @@ -24,19 +24,6 @@ void sdelay(unsigned long loops) "bne 1b":"=r" (loops):"0"(loops)); } -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = readl((u32)addr) & ~(msk << start_bit); - tmp |= value << start_bit; - writel(tmp, (u32)addr); -} - /********************************************************************* * wait_on_value() - common routine to allow waiting for changes in * volatile regs. |