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author | Minkyu Kang <mk7.kang@samsung.com> | 2014-10-07 10:14:03 (GMT) |
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committer | Minkyu Kang <mk7.kang@samsung.com> | 2014-10-07 10:14:03 (GMT) |
commit | 3cc83f9d08a80fddf4c1e8e766eff8273f30814c (patch) | |
tree | 831246a1b77d26d0296a84c90684e0fee0368737 /arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c | |
parent | 64f41212d880f3d00c6994d973aadeec5bda1b65 (diff) | |
parent | 6dd0e7c00bfa5ce861a72b8e4a3ef9e787306125 (diff) | |
download | u-boot-3cc83f9d08a80fddf4c1e8e766eff8273f30814c.tar.xz |
Merge branch 'uboot'
Diffstat (limited to 'arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c')
-rw-r--r-- | arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c new file mode 100644 index 0000000..a37ed16 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sbc-regs.h> +#include <asm/arch/sg-regs.h> + +void sbc_init(void) +{ + /* XECS1: sub/boot memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); + +#if !defined(CONFIG_SPL_BUILD) + /* XECS0: boot/sub memory (boot swap = off/on) */ + writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); + writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); + writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); + writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); +#endif + /* XECS3: peripherals */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); + + /* base address regsiters */ + writel(0x0000bc01, SBBASE0); + writel(0x0400bc01, SBBASE1); + writel(0x0800bf01, SBBASE3); + +#if !defined(CONFIG_SPL_BUILD) + /* enable access to sub memory when boot swap is on */ + sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ +#endif + sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ +} |