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| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2017-07-20 04:22:43 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-08-23 04:12:21 (GMT) |
| commit | 61b9068c8ddb1d5e7693146731e080ed95097954 (patch) | |
| tree | 4ce906865fea787e90104b972db97044d565e618 /arch/arm/cpu/armv7 | |
| parent | 75f98d57107a571de852d0d383833ac2b1bda0cd (diff) | |
| download | u-boot-61b9068c8ddb1d5e7693146731e080ed95097954.tar.xz | |
armv7: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters.
This patch add new CONFIG defination "FSL_SYS_HAS_CCI400" and
removes register space definaton of CCI-400 bus from
immap_ls102xa to fsl_immap, since same is defined there already
"CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET
is introduced in Kconfig
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 12 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/soc.c | 3 |
2 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 78b6ada..fd57cae 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -5,6 +5,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_HAS_CCI400 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -52,9 +53,20 @@ config SECURE_BOOT Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. +config SYS_CCI400_OFFSET + hex "Offset for CCI400 base" + depends on SYS_FSL_HAS_CCI400 + default 0x180000 + help + Offset for CCI400 base. + CCI400 base addr = CCSRBAR + CCI400_OFFSET + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" +config SYS_FSL_HAS_CCI400 + bool + config SYS_FSL_SRDS_1 bool diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b14be47..7bb67c8 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -125,7 +125,8 @@ void erratum_a010315(void) int arch_soc_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); unsigned int major; #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |