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| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2017-08-16 13:50:31 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-08-23 04:12:21 (GMT) |
| commit | 5ca57bcdc7573e39015ee181f19e9dcbbd72199c (patch) | |
| tree | a2c811fd9dc93cec96afbe6b4bbc4f990dc0beab /arch/arm/cpu/armv8/fsl-layerscape/Kconfig | |
| parent | aca7df320f4a01bea8c7cf045b274d83273ecf00 (diff) | |
| download | u-boot-5ca57bcdc7573e39015ee181f19e9dcbbd72199c.tar.xz | |
armv8: fsl-lsch3: Make CCN-504 related code conditional
LS2080 family has CCN-504 cache coherent interconnet.
Other SoCs from LSCH3 may have differnt interconnect like
LS1088.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/Kconfig')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index c44b2c3..2f8d9da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -72,6 +72,7 @@ config ARCH_LS2080A select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_CCN504 select SYS_FSL_HAS_DP_DDR select SYS_FSL_HAS_SEC select SYS_FSL_HAS_DDR4 @@ -289,6 +290,9 @@ config SYS_FSL_IFC_BANK_COUNT config SYS_FSL_HAS_CCI400 bool +config SYS_FSL_HAS_CCN504 + bool + config SYS_FSL_HAS_DP_DDR bool |