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authorAshish Kumar <Ashish.Kumar@nxp.com>2017-08-10 06:00:20 (GMT)
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2017-08-23 04:12:21 (GMT)
commit75f98d57107a571de852d0d383833ac2b1bda0cd (patch)
tree83c71ca2759098f662e8a57110eb0eef3dc9525d /arch/arm/cpu/armv8/fsl-layerscape/Kconfig
parent8e34f1023816f7b864a5dde8be10221892acb86f (diff)
downloadu-boot-75f98d57107a571de852d0d383833ac2b1bda0cd.tar.xz
armv8:fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and moves existing register space definaton of CCI-400 bus from immap_lsch2 to fsl_immap, so that it can be used for both chasis 2 and chasis 3. "CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET is introduced in Kconfig Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/Kconfig')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 77ba041..c44b2c3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -99,6 +99,7 @@ config ARCH_LS2080A
config FSL_LSCH2
bool
+ select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_BE
@@ -269,6 +270,15 @@ config QSPI_AHB_INIT
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
bus for those flashes to support the full QSPI flash size.
+config SYS_CCI400_OFFSET
+ hex "Offset for CCI400 base"
+ depends on SYS_FSL_HAS_CCI400
+ default 0x3090000 if ARCH_LS1088A
+ default 0x180000 if FSL_LSCH2
+ help
+ Offset for CCI400 base
+ CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
@@ -276,6 +286,9 @@ config SYS_FSL_IFC_BANK_COUNT
default 4 if ARCH_LS1046A
default 8 if ARCH_LS2080A
+config SYS_FSL_HAS_CCI400
+ bool
+
config SYS_FSL_HAS_DP_DDR
bool