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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2017-01-06 09:41:11 (GMT)
committerYork Sun <york.sun@nxp.com>2017-01-18 17:27:53 (GMT)
commitee2a51022135a01fa2258b7788702313d0f54dac (patch)
tree4d773ba8001bfc4f7e856ca1e203ab8827ce1c98 /arch/arm/cpu/armv8/fsl-layerscape/Kconfig
parent3aec452e4dbd16be7bdbabfa80d1fcc840cf342c (diff)
downloadu-boot-ee2a51022135a01fa2258b7788702313d0f54dac.tar.xz
ARMv8/fsl-layerscape: Enable data coherency between cores in cluster
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/Kconfig')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9d37b2f..7572f19 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,5 +1,6 @@
config ARCH_LS1012A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH2
select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
@@ -7,6 +8,7 @@ config ARCH_LS1012A
config ARCH_LS1043A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH2
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
@@ -23,6 +25,7 @@ config ARCH_LS1043A
config ARCH_LS1046A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH2
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
@@ -38,6 +41,7 @@ config ARCH_LS1046A
config ARCH_LS2080A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH3
select SYS_FSL_DDR
select SYS_FSL_DDR_LE