diff options
author | York Sun <york.sun@nxp.com> | 2016-04-04 18:41:26 (GMT) |
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committer | York Sun <york.sun@nxp.com> | 2016-04-06 17:26:46 (GMT) |
commit | 3c1d218a1d3048fb576677c47eab43049d0b7778 (patch) | |
tree | fac5c6482522cef5563f368ee2777f4ed274759e /arch/arm/cpu/armv8/fsl-layerscape/cpu.c | |
parent | 2a5558399828e24fce9e948288a88cd28887875e (diff) | |
download | u-boot-3c1d218a1d3048fb576677c47eab43049d0b7778.tar.xz |
armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/cpu.c')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 4b9e209..d939900 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -538,12 +538,12 @@ int print_cpuinfo(void) struct sys_info sysinfo; char buf[32]; unsigned int i, core; - u32 type, rcw; + u32 type, rcw, svr = gur_in32(&gur->svr); puts("SoC: "); cpu_name(buf); - printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr)); + printf(" %s (0x%x)\n", buf, svr); memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); get_sys_info(&sysinfo); puts("Clock Configuration:"); @@ -564,7 +564,10 @@ int print_cpuinfo(void) printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); #endif #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); + if (soc_has_dp_ddr()) { + printf(" DP-DDR: %-4s MT/s", + strmhz(buf, sysinfo.freq_ddrbus2)); + } #endif puts("\n"); |