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| author | Alison Wang <b18965@freescale.com> | 2016-07-05 08:01:52 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-07-26 16:02:00 (GMT) |
| commit | 79119a4d1930468c47da5d000c41751a92bcaa62 (patch) | |
| tree | aae4b42ddf0f70fcbf741f9cfc38a1889bc0c91d /arch/arm/cpu/armv8/fsl-layerscape/cpu.c | |
| parent | dbb9d04fbd4c65243ddff1b1ccd0b50274ad777b (diff) | |
| download | u-boot-79119a4d1930468c47da5d000c41751a92bcaa62.tar.xz | |
armv8: fsl-layerscape: Add A72 core detection
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/cpu.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 7a2ec6b..eaff166 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -309,7 +309,8 @@ int print_cpuinfo(void) printf("CPU%d(%s):%-4s MHz ", core, type == TY_ITYP_VER_A7 ? "A7 " : (type == TY_ITYP_VER_A53 ? "A53" : - (type == TY_ITYP_VER_A57 ? "A57" : " ")), + (type == TY_ITYP_VER_A57 ? "A57" : + (type == TY_ITYP_VER_A72 ? "A72" : " "))), strmhz(buf, sysinfo.freq_processor[core])); } printf("\n Bus: %-4s MHz ", |