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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2015-11-05 06:30:14 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-11-30 17:11:12 (GMT) |
| commit | b4017364630fbc526bbf5e917d8fae6013805488 (patch) | |
| tree | ea2df6ef79c7526db3f91e1cfb06803b3e96aebd /arch/arm/cpu/armv8/fsl-layerscape/cpu.c | |
| parent | 5380335e66e7d731bd417f0fe6fcee68750b0245 (diff) | |
| download | u-boot-b4017364630fbc526bbf5e917d8fae6013805488.tar.xz | |
armv8: ls2085a: Add workaround of errata A009635
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/cpu.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 571ee7b..8847fc0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -484,7 +484,13 @@ int arch_early_init_r(void) { #ifdef CONFIG_MP int rv = 1; +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 + erratum_a009635(); +#endif +#ifdef CONFIG_MP rv = fsl_layerscape_wake_seconday_cores(); if (rv) printf("Did not wake secondary cores\n"); |