diff options
| author | York Sun <york.sun@nxp.com> | 2016-06-24 23:46:18 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-07-15 16:01:43 (GMT) |
| commit | e61a7534e33063a76e105d895e5c6317f2d0cd76 (patch) | |
| tree | 4dc7e8f638a6b412256c6e052bc9490ac91a7792 /arch/arm/cpu/armv8/fsl-layerscape/cpu.c | |
| parent | 3a592a1349ac3961b0f4f2db0a8d9f128225d897 (diff) | |
| download | u-boot-e61a7534e33063a76e105d895e5c6317f2d0cd76.tar.xz | |
armv8: Move secure_ram variable out of generic global data
Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/cpu.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 8062106..a397f5d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -289,8 +289,8 @@ static inline int final_secure_ddr(u64 *level0_table, * These tables are in DRAM. Sub tables are added to enable cache for * QBMan and OCRAM. * - * Put the MMU table in secure memory if gd->secure_ram is valid. - * OCRAM will be not used for this purpose so gd->secure_ram can't be 0. + * Put the MMU table in secure memory if gd->arch.secure_ram is valid. + * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. * * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. @@ -321,13 +321,13 @@ static inline void final_mmu_setup(void) if (el == 3) { /* - * Only use gd->secure_ram if the address is recalculated + * Only use gd->arch.secure_ram if the address is recalculated * Align to 4KB for MMU table */ - if (gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) - level0_table = (u64 *)(gd->secure_ram & ~0xfff); + if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) + level0_table = (u64 *)(gd->arch.secure_ram & ~0xfff); else - printf("MMU warning: gd->secure_ram is not maintained, disabled.\n"); + printf("MMU warning: gd->arch.secure_ram is not maintained, disabled.\n"); } #endif level1_table0 = level0_table + 512; @@ -374,7 +374,7 @@ static inline void final_mmu_setup(void) } /* Set the secure memory to secure in MMU */ #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - if (el == 3 && gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { + if (el == 3 && gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { #ifdef CONFIG_FSL_LSCH3 level2_table_secure = level2_table1 + 512; #elif defined(CONFIG_FSL_LSCH2) @@ -382,10 +382,10 @@ static inline void final_mmu_setup(void) #endif if (!final_secure_ddr(level0_table, level2_table_secure, - gd->secure_ram & ~0x3)) { - gd->secure_ram |= MEM_RESERVE_SECURE_SECURED; + gd->arch.secure_ram & ~0x3)) { + gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; debug("Now MMU table is in secured memory at 0x%llx\n", - gd->secure_ram & ~0x3); + gd->arch.secure_ram & ~0x3); } else { printf("MMU warning: Failed to secure DDR\n"); } |