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| author | Priyanka Jain <priyanka.jain@nxp.com> | 2016-11-17 06:59:56 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-11-22 19:38:48 (GMT) |
| commit | e87c673c206aa3eb75eb94e65d8d50d7fabaf598 (patch) | |
| tree | 04e110309a4deebba7e05dcf1be7881e6cf2b791 /arch/arm/cpu/armv8/fsl-layerscape/cpu.c | |
| parent | 9ae836cde7aa8f54ee06879b1653b7260f866629 (diff) | |
| download | u-boot-e87c673c206aa3eb75eb94e65d8d50d7fabaf598.tar.xz | |
armv8/fsl-lsch3: Update code to release secondary cores
NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
But other new SoCs like LS2088A, LS1088A release secondary
cores one by one.
Update code to release secondary cores based on SoC SVR
Add code to release cores one by one for non LS2080A SoCs
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: remove "inline" from declaration of initiator_type]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/cpu.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index eb03bf4..d6ee546 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -191,7 +191,7 @@ void enable_caches(void) } #endif -static inline u32 initiator_type(u32 cluster, int init_id) +u32 initiator_type(u32 cluster, int init_id) { struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; |