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authorRajesh Bhagat <rajesh.bhagat@nxp.com>2017-08-25 06:52:39 (GMT)
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2017-08-30 09:52:30 (GMT)
commit836e9d24ad833594fca1677dbe476abb65aff60b (patch)
tree70143834c7ae4f3e822cebe0da7bde85a5c0f43c /arch/arm/cpu/armv8/fsl-layerscape/soc.c
parent51e5f9c51bfc679b2c236a795f0c260a6d42a00b (diff)
downloadu-boot-836e9d24ad833594fca1677dbe476abb65aff60b.tar.xz
armv8: lsch3: Add serdes and DDR voltage setup
Adds SERDES voltage and reset SERDES lanes API and makes enable/disable DDR controller support 0.9V API common. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/soc.c')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c34
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7c26953..42d6ad6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -545,23 +545,6 @@ static int setup_core_volt(u32 vdd)
return board_setup_core_volt(vdd);
}
-#ifdef CONFIG_SYS_FSL_DDR
-static void ddr_enable_0v9_volt(bool en)
-{
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
- u32 tmp;
-
- tmp = ddr_in32(&ddr->ddr_cdr1);
-
- if (en)
- tmp |= DDR_CDR1_V0PT9_EN;
- else
- tmp &= ~DDR_CDR1_V0PT9_EN;
-
- ddr_out32(&ddr->ddr_cdr1, tmp);
-}
-#endif
-
int setup_chip_volt(void)
{
int vdd;
@@ -630,6 +613,23 @@ void fsl_lsch2_early_init_f(void)
}
#endif
+#ifdef CONFIG_SYS_FSL_DDR
+void ddr_enable_0v9_volt(bool en)
+{
+ struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ u32 tmp;
+
+ tmp = ddr_in32(&ddr->ddr_cdr1);
+
+ if (en)
+ tmp |= DDR_CDR1_V0PT9_EN;
+ else
+ tmp &= ~DDR_CDR1_V0PT9_EN;
+
+ ddr_out32(&ddr->ddr_cdr1, tmp);
+}
+#endif
+
#ifdef CONFIG_QSPI_AHB_INIT
/* Enable 4bytes address support and fast read */
int qspi_ahb_init(void)