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| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2017-07-20 04:22:43 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-08-23 04:12:21 (GMT) |
| commit | 61b9068c8ddb1d5e7693146731e080ed95097954 (patch) | |
| tree | 4ce906865fea787e90104b972db97044d565e618 /arch/arm/cpu/armv8/fsl-layerscape | |
| parent | 75f98d57107a571de852d0d383833ac2b1bda0cd (diff) | |
| download | u-boot-61b9068c8ddb1d5e7693146731e080ed95097954.tar.xz | |
armv7: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters.
This patch add new CONFIG defination "FSL_SYS_HAS_CCI400" and
removes register space definaton of CCI-400 bus from
immap_ls102xa to fsl_immap, since same is defined there already
"CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET
is introduced in Kconfig
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape')
0 files changed, 0 insertions, 0 deletions