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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2016-08-02 11:03:27 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-09-14 21:07:13 (GMT) |
| commit | b392a6d4b05b7409283cd75b4ac6bd12018d187a (patch) | |
| tree | 272b0b5b8780f23ed8fc102d09c97d94c9dbe7e6 /arch/arm/cpu/armv8/fsl-layerscape | |
| parent | 664b6520582fcea7e150f57258c7a63627837318 (diff) | |
| download | u-boot-b392a6d4b05b7409283cd75b4ac6bd12018d187a.tar.xz | |
fsl-layerscape: Add workaround for PCIe erratum A010315
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 2b39a02..43c4aa5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -8,11 +8,14 @@ #include <fsl_ifc.h> #include <ahci.h> #include <scsi.h> +#include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS #include <fsl_csu.h> +#endif #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr_sdram.h> #include <fsl_ddr.h> @@ -301,6 +304,19 @@ void erratum_a008850_post(void) #endif } +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void) +{ + int i; + + for (i = PCIE1; i <= PCIE4; i++) + if (!is_serdes_configured(i)) { + debug("PCIe%d: disabled all R/W permission!\n", i); + set_pcie_ns_access(i, 0); + } +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; |