diff options
author | Ran Wang <ran.wang_1@nxp.com> | 2017-06-17 09:28:42 (GMT) |
---|---|---|
committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-08-17 11:29:08 (GMT) |
commit | 7b13b78d9592d1811b8775f0fd4cebebdf1973df (patch) | |
tree | 582d18b4460a9ffad64d7880093e26aafb5322d2 /arch/arm/cpu/armv8 | |
parent | 39aba2257d019528a9c05085634ac50981862bc5 (diff) | |
download | u-boot-7b13b78d9592d1811b8775f0fd4cebebdf1973df.tar.xz |
arm: Fix USB errata reilated patches issue.
1.Miss definition in Kconfig.
2.Compile switch should be CONFIG_ARCH_LSxxx.
3.Miss some register define.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 14 |
2 files changed, 19 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a14708d..77ba041 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -407,6 +407,18 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool +config SYS_FSL_ERRATUM_A009007 + bool + +config SYS_FSL_ERRATUM_A008997 + bool + +config SYS_FSL_ERRATUM_A009798 + bool + +config SYS_FSL_ERRATUM_A009008 + bool + config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index c5ea47d..d66ee1a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; static void erratum_a009008(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 -#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4); val &= ~(0xF << 6); @@ -53,7 +53,7 @@ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6)); static void erratum_a009798(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 -#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4); scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE); @@ -61,7 +61,7 @@ val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4); scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE); val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4); scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE); -#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#elif defined(CONFIG_ARCH_LS2080A) u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4); scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE); @@ -72,7 +72,7 @@ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE); static void erratum_a008997(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 -#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4); val &= ~(0x7F << 9); @@ -86,7 +86,7 @@ static void erratum_a008997(void) val &= ~(0x7F << 9); scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4, val | (USB_PCSTXSWINGFULL << 9)); -#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#elif defined(CONFIG_ARCH_LS2080A) u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4); val &= ~(0x7F << 9); @@ -100,7 +100,7 @@ static void erratum_a009007(void) { /* TODO:implement the out_be16 instead of writew which is taking little endian style */ -#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY1; writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); @@ -116,7 +116,7 @@ little endian style */ writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI); -#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#elif defined(CONFIG_ARCH_LS2080A) u32 __iomem *dcsr = (u32 __iomem *)DCSR_BASE; writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI); |