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author | vishnupatekar <vishnupatekar0510@gmail.com> | 2015-11-28 17:07:24 (GMT) |
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committer | Hans de Goede <hdegoede@redhat.com> | 2015-12-10 14:45:47 (GMT) |
commit | f542948b1e8cd53d6e48e38bae6e305233b9d7a3 (patch) | |
tree | 0b16908f2d880ec1bc591f9a5d4e5884daaa01e4 /arch/arm/cpu | |
parent | 95ab8fee8a5b1782d554be9565584eb29e7da0ce (diff) | |
download | u-boot-f542948b1e8cd53d6e48e38bae6e305233b9d7a3.tar.xz |
sunxi: clk: add basic clocks for A83T
Add basic clocks pll1, pll5, and some default values from allwinner u-boot.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz,
fixing the mmc support not working
[hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to
stabilize, fixing cold-booting directly from sdcard not working
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/Makefile | 4 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c | 136 |
2 files changed, 140 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index e4b33ce..d243b9e 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -26,7 +26,11 @@ obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o +ifdef CONFIG_MACH_SUN8I_A83T +obj-y += clock_sun8i_a83t.o +else obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o +endif obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o obj-$(CONFIG_MACH_SUN6I) += tzpc.o diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c new file mode 100644 index 0000000..3e8728f --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock_sun8i_a83t.c @@ -0,0 +1,136 @@ +/* + * A83 specific clock code + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/prcm.h> +#include <asm/arch/sys_proto.h> + +#ifdef CONFIG_SPL_BUILD +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + clock_set_pll1(408000000); + /* enable pll_hsic, default is 480M */ + writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg); + writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); + while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {} + + /* switch to default 24MHz before changing to hsic */ + writel(0x0, &ccm->cci400_cfg); + sdelay(50); + writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg); + sdelay(100); + + /* switch before changing pll6 */ + clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK, + AHB1_CLK_SRC_OSC24M); + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); + while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {} + + writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); + writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset); + writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg); + + /* timestamp */ + writel(1, 0x01720000); +} +#endif + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* uart clock source is apb2 */ + writel(APB2_CLK_SRC_OSC24M| + APB2_CLK_RATE_N_1| + APB2_CLK_RATE_M(1), + &ccm->apb2_div); + + /* open the clock for uart */ + setbits_le32(&ccm->apb2_gate, + CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + + /* deassert uart reset */ + setbits_le32(&ccm->apb2_reset_cfg, + 1 << (APB2_RESET_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); +} + +#ifdef CONFIG_SPL_BUILD +void clock_set_pll1(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_2 << AXI0_DIV_SHIFT | + AXI_DIV_2 << AXI1_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT | + CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); + + /* clk = 24*n/p, p is ignored if clock is >288MHz */ + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 | + CCM_PLL1_CTRL_N(clk / 24000000), + &ccm->pll1_c0_cfg); + while (!(readl(&ccm->pll_stable_status) & 0x01)) {} + + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 | + CCM_PLL1_CTRL_N(clk / (24000000)), + &ccm->pll1_c1_cfg); + while (!(readl(&ccm->pll_stable_status) & 0x02)) {} + + /* Switch CPU to PLL1 */ + writel(AXI_DIV_2 << AXI0_DIV_SHIFT | + AXI_DIV_2 << AXI1_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT | + CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); +} +#endif + +void clock_set_pll5(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + unsigned int div1 = 0, div2 = 0; + + /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */ + writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD | + CCM_PLL5_CTRL_N(clk / (24000000)) | + div2 << CCM_PLL5_DIV2_SHIFT | + div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg); + + udelay(5500); +} + + +unsigned int clock_get_pll6(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + uint32_t rval = readl(&ccm->pll6_cfg); + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); + int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> + CCM_PLL6_CTRL_DIV1_SHIFT) + 1; + int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> + CCM_PLL6_CTRL_DIV2_SHIFT) + 1; + return 24000000 * n / div1 / div2; +} |