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| author | maxims@google.com <maxims@google.com> | 2017-04-17 19:00:25 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-05-08 15:57:32 (GMT) |
| commit | c93adc08f393bc401c5929e1045d72dfbea3e126 (patch) | |
| tree | fca83951bf57a75fa26c2069272a3dded7a0c0ea /arch/arm/dts/ast2500-u-boot.dtsi | |
| parent | 858d4976293f0b3d72e5dcf0e8a1a973efafeee3 (diff) | |
| download | u-boot-c93adc08f393bc401c5929e1045d72dfbea3e126.tar.xz | |
aspeed: Device Tree configuration for Reset Driver
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/dts/ast2500-u-boot.dtsi')
| -rw-r--r-- | arch/arm/dts/ast2500-u-boot.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index c95a7ba..faeeec1 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -1,4 +1,5 @@ #include <dt-bindings/clock/ast2500-scu.h> +#include <dt-bindings/reset/ast2500-reset.h> #include "ast2500.dtsi" @@ -11,12 +12,21 @@ #reset-cells = <1>; }; + rst: reset-controller { + u-boot,dm-pre-reloc; + compatible = "aspeed,ast2500-reset"; + aspeed,wdt = <&wdt1>; + #reset-cells = <1>; + }; + sdrammc: sdrammc@1e6e0000 { u-boot,dm-pre-reloc; compatible = "aspeed,ast2500-sdrammc"; reg = <0x1e6e0000 0x174 0x1e6e0200 0x1d4 >; + #reset-cells = <1>; clocks = <&scu PLL_MPLL>; + resets = <&rst AST_RESET_SDRAM>; }; ahb { |