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| author | Jagan Teki <jagan@openedev.com> | 2017-02-24 10:15:21 (GMT) |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2017-03-17 08:27:08 (GMT) |
| commit | baa0920dcb405a479218e7164ee9681a497a18f2 (patch) | |
| tree | 671b3e7f30a25a74eb1b726f7b93dc012a41725d /arch/arm/dts/imx6qdl-icore-rqs.dtsi | |
| parent | e9685967bbcdbf9ca8bd5e313b747a02d0b0ca07 (diff) | |
| download | u-boot-baa0920dcb405a479218e7164ee9681a497a18f2.tar.xz | |
arm: dts: imx6qdl-icore-rqs: Add eMMC node
Add usdhc4 node, which is eMMC for Engicam i.CoreM6 RQS modules.
eMMC Log:
--------
icorem6qdl-rqs> mmc dev 1
switch to partitions #0, OK
mmc1(part 0) is current device
icorem6qdl-rqs> mmcinfo
Device: FSL_SDHC
Manufacturer ID: fe
OEM: 14e
Name: MMC04
Tran Speed: 52000000
Rd Block Len: 512
MMC version 4.4.1
High Capacity: Yes
Capacity: 3.5 GiB
Bus Width: 4-bit
Erase Group Size: 512 KiB
HC WP Group Size: 4 MiB
User Capacity: 3.5 GiB
Boot Capacity: 16 MiB ENH
RPMB Capacity: 128 KiB ENH
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/arm/dts/imx6qdl-icore-rqs.dtsi')
| -rw-r--r-- | arch/arm/dts/imx6qdl-icore-rqs.dtsi | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi index 750229b..8b9d5b4 100644 --- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi @@ -107,6 +107,13 @@ status = "okay"; }; +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + no-1-8-v; + status = "okay"; +}; + &iomuxc { pinctrl_enet: enetgrp { fsl,pins = < @@ -167,4 +174,19 @@ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 >; }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070 + >; + }; }; |