diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2017-02-22 08:56:36 (GMT) |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-03-16 22:03:46 (GMT) |
| commit | a82426e07319dcd76881370ba64d4dcd7c2e8312 (patch) | |
| tree | c8785f7d7f4c3270b7965b0552ee00d19cee1959 /arch/arm/dts/rk3399.dtsi | |
| parent | fa437430ad9861886f5766151757a99de647d086 (diff) | |
| download | u-boot-a82426e07319dcd76881370ba64d4dcd7c2e8312.tar.xz | |
rockchip: dts: rk3399: update for spl require driver
Add syscon and dmc node, and 'u-boot,dm-pre-reloc' option for
required driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/dts/rk3399.dtsi')
| -rw-r--r-- | arch/arm/dts/rk3399.dtsi | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 22277ff..379e04b 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -183,6 +183,7 @@ }; sdhci: sdhci@fe330000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; @@ -416,6 +417,7 @@ }; pmugrf: syscon@ff320000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff320000 0x0 0x1000>; #address-cells = <1>; @@ -427,6 +429,12 @@ }; }; + pmusgrf: syscon@ff330000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-pmusgrf", "syscon"; + reg = <0x0 0xff330000 0x0 0xe3d4>; + }; + spi3: spi@ff350000 { compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; reg = <0x0 0xff350000 0x0 0x1000>; @@ -497,7 +505,40 @@ status = "disabled"; }; + cic: syscon@ff620000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-cic", "syscon"; + reg = <0x0 0xff620000 0x0 0x100>; + }; + + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: dmc { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + reg = <0x0 0xffa80000 0x0 0x0800 + 0x0 0xffa80800 0x0 0x1800 + 0x0 0xffa82000 0x0 0x2000 + 0x0 0xffa84000 0x0 0x1000 + 0x0 0xffa88000 0x0 0x0800 + 0x0 0xffa88800 0x0 0x1800 + 0x0 0xffa8a000 0x0 0x2000 + 0x0 0xffa8c000 0x0 0x1000>; + }; + pmucru: pmu-clock-controller@ff750000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; #clock-cells = <1>; @@ -507,6 +548,7 @@ }; cru: clock-controller@ff760000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; #clock-cells = <1>; @@ -530,6 +572,7 @@ }; grf: syscon@ff770000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; @@ -607,6 +650,7 @@ }; pinctrl: pinctrl { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3399-pinctrl"; rockchip,grf = <&grf>; rockchip,pmu = <&pmugrf>; |