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authorVikas Manocha <vikas.manocha@st.com>2017-02-12 18:25:52 (GMT)
committerTom Rini <trini@konsulko.com>2017-03-17 18:15:16 (GMT)
commitc428a9583349f75f404750253920620207f70d55 (patch)
treee7ecb0052defc132a19ee15979929388b3a2d950 /arch/arm/dts/stm32f746.dtsi
parente34e19feb7d06c2c0baf28ed145fe8f63b166fc8 (diff)
downloadu-boot-c428a9583349f75f404750253920620207f70d55.tar.xz
ARM: DT: stm32f7: add ethernet pin contol node
It also removes the ethernet pin configuration done during the board initialization. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'arch/arm/dts/stm32f746.dtsi')
-rw-r--r--arch/arm/dts/stm32f746.dtsi14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 867f399..431e79c 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -117,6 +117,20 @@
bias-disable;
};
};
+ ethernet_mii: mii@0 {
+ pins {
+ pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+ <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+ <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+ <STM32F746_PA2_FUNC_ETH_MDIO>,
+ <STM32F746_PC1_FUNC_ETH_MDC>,
+ <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+ <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+ <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+ <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+ slew-rate = <2>;
+ };
+ };
};
};
};