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| author | Vikas Manocha <vikas.manocha@st.com> | 2017-02-12 18:25:53 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-03-17 18:15:16 (GMT) |
| commit | e245f1a5db086d676cbd97371046ea5c5e554326 (patch) | |
| tree | 5244751424de78b7abd63dd22eaf7010893045f8 /arch/arm/dts/stm32f746.dtsi | |
| parent | c428a9583349f75f404750253920620207f70d55 (diff) | |
| download | u-boot-e245f1a5db086d676cbd97371046ea5c5e554326.tar.xz | |
ARM: DT: stm32f7: add qspi pin contol node
It also removes the qspi pin configuration done during the
board initialization.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'arch/arm/dts/stm32f746.dtsi')
| -rw-r--r-- | arch/arm/dts/stm32f746.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 431e79c..b2b0b5f 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -131,6 +131,17 @@ slew-rate = <2>; }; }; + qspi_pins: qspi@0{ + pins { + pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, + <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, + <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, + <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, + <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, + <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; + slew-rate = <2>; + }; + }; }; }; }; |