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authorStephen Warren <swarren@nvidia.com>2016-09-12 17:51:14 (GMT)
committerJoe Hershberger <joe.hershberger@ni.com>2016-11-07 17:28:16 (GMT)
commit31c1ff90e2070759dd8c35a182f96c342543dad6 (patch)
tree879d714510e58eac2f4a54eb3b290e1945704507 /arch/arm/dts/tegra186.dtsi
parent2b950f3aea8a3a222de661e99b8a4a029dbb9cca (diff)
downloadu-boot-31c1ff90e2070759dd8c35a182f96c342543dad6.tar.xz
ARM: tegra: add DWC EQoS (ethernet) to Tegra186 DT
Tegra186 includes a Synopsys DWC EQoS (Ethernet) device. Add this to the Tegra186 SoC DT so that boards can make use of it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'arch/arm/dts/tegra186.dtsi')
-rw-r--r--arch/arm/dts/tegra186.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
index f878b65..dd9e3b8 100644
--- a/arch/arm/dts/tegra186.dtsi
+++ b/arch/arm/dts/tegra186.dtsi
@@ -31,6 +31,26 @@
#interrupt-cells = <2>;
};
+ ethernet@2490000 {
+ compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10";
+ reg = <0x0 0x02490000 0x0 0x10000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
+ <&bpmp TEGRA186_CLK_EQOS_AXI>,
+ <&bpmp TEGRA186_CLK_EQOS_RX>,
+ <&bpmp TEGRA186_CLK_EQOS_PTP_REF>,
+ <&bpmp TEGRA186_CLK_EQOS_TX>;
+ clock-names = "slave_bus",
+ "master_bus",
+ "rx",
+ "ptp_ref",
+ "tx";
+ resets = <&bpmp TEGRA186_RESET_EQOS>;
+ reset-names = "eqos";
+ phy-mode = "rgmii";
+ status = "disabled";
+ };
+
uarta: serial@3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x10000>;