ARM: tegra: pull Tegra30 SoC DT from Linux v4.7

The primary benefit of this change is that it adds all missing clocks and
resets properties to peripherals. This will allow peripheral drivers to
migrate to the standard clock and reset APIs in the future.

Main changes:
* Modification of PCIe memory region addresses. The HW memory layout is
  programmable, so this should work fine, and Beaver PCIe was tested
  without issue.
* Removal of pcie_xclk from the PCIe node and clock binding header. This
  clock doesn't exist and isn't used; only a reset with this ID exists.
* Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use
  DMA so isn't affected.
* Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all
  information required by U-Boot, so U-Boot is not affected.
* Changed the phy_type value for the second USB port. This required board
  DTs to be updated to keep the same configuration.
* Boards need to define the clk32k_in clock that feeds the Tegra PMC.
* Addition of tegra30-mc.h since tegra30.dtsi now includes it.
* Conversion of many magic numbers to named defines.
* Addition of many nodes not used by U-Boot.
* Node sort order fixes.

Remaining deltas relative to the Linux DT:
* None.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

1 files changed, 20 insertions, 1 deletions

diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 60e87a4..f83f094 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -277,7 +277,6 @@
 		status = "okay";
 		/* USBH_EN */
 		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
-		phy_type = "utmi";
 	};
 
 	/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
@@ -287,6 +286,26 @@
 		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
 	};
 
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk32k_in: clk@0 {
+			compatible = "fixed-clock";
+			reg=<0>;
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+		clk16m: clk@1 {
+			compatible = "fixed-clock";
+			reg=<1>;
+			#clock-cells = <0>;
+			clock-frequency = <16000000>;
+			clock-output-names = "clk16m";
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;