diff options
author | Kever Yang <kever.yang@rock-chips.com> | 2017-02-23 07:37:50 (GMT) |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2017-03-16 22:03:46 (GMT) |
commit | e94ffee335f23d86cad0f8816b049bb4100d5be3 (patch) | |
tree | a169405cbd7d78a8d186de0c5ff17aad73a08d3b /arch/arm/dts | |
parent | 66e87cc842e1a57cb2d666966fd9b250ca2f6e05 (diff) | |
download | u-boot-e94ffee335f23d86cad0f8816b049bb4100d5be3.tar.xz |
rockchip: rk3328: add device tree file
Add dts binding header for rk3328, files origin from kernel.
Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/dts')
-rw-r--r-- | arch/arm/dts/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/dts/rk3328-evb.dts | 45 | ||||
-rw-r--r-- | arch/arm/dts/rk3328.dtsi | 1477 |
3 files changed, 1523 insertions, 0 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 231ebfa..d00651c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-fennec.dtb \ rk3288-tinker.dtb \ rk3288-popmetal.dtb \ + rk3328-evb.dtb \ rk3399-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts new file mode 100644 index 0000000..01794ed --- /dev/null +++ b/arch/arm/dts/rk3328-evb.dts @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Rockchip RK3328 EVB"; + compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; + + chosen { + stdout-path = &uart2; + }; +}; + +&uart2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + supports-emmc; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi new file mode 100644 index 0000000..8a98ee3 --- /dev/null +++ b/arch/arm/dts/rk3328.dtsi @@ -0,0 +1,1477 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/rk3328-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> + +/ { + compatible = "rockchip,rk3328"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; +// clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + }; + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <40000>; + }; + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <40000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1225000>; + clock-latency-ns = <40000>; + }; + opp@1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1300000>; + clock-latency-ns = <40000>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + i2s0: i2s@ff000000 { + compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff000000 0x0 0x1000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 11>, <&dmac 12>; + #dma-cells = <2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s1: i2s@ff010000 { + compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff010000 0x0 0x1000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 14>, <&dmac 15>; + #dma-cells = <2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s2: i2s@ff020000 { + compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff020000 0x0 0x1000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 0>, <&dmac 1>; + #dma-cells = <2>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2m0_mclk + &i2s2m0_sclk + &i2s2m0_lrcktx + &i2s2m0_lrckrx + &i2s2m0_sdo + &i2s2m0_sdi>; + pinctrl-1 = <&i2s2m0_sleep>; + status = "disabled"; + }; + + spdif: spdif@ff030000 { + compatible = "rockchip,rk3328-spdif"; + reg = <0x0 0xff030000 0x0 0x1000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 10>; + #dma-cells = <1>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm2_tx>; + status = "disabled"; + }; + + grf: syscon@ff100000 { + compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff100000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + io_domains: io-domains { + compatible = "rockchip,rk3328-io-voltage-domain"; + status = "disabled"; + }; + }; + + uart0: serial@ff110000 { + compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff110000 0x0 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 2>, <&dmac 3>; + #dma-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + uart1: serial@ff120000 { + compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff120000 0x0 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "sclk_uart", "pclk_uart"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 4>, <&dmac 5>; + #dma-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; + status = "disabled"; + }; + + uart2: serial@ff130000 { + compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff130000 0x0 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 6>, <&dmac 7>; + #dma-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "disabled"; + }; + + pmu: power-management@ff140000 { + compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff140000 0x0 0x1000>; + }; + + i2c0: i2c@ff150000 { + compatible = "rockchip,rk3328-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + i2c1: i2c@ff160000 { + compatible = "rockchip,rk3328-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c2: i2c@ff170000 { + compatible = "rockchip,rk3328-i2c"; + reg = <0x0 0xff170000 0x0 0x1000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + i2c3: i2c@ff180000 { + compatible = "rockchip,rk3328-i2c"; + reg = <0x0 0xff180000 0x0 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + spi0: spi@ff190000 { + compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff190000 0x0 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 8>, <&dmac 9>; + #dma-cells = <2>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; + status = "disabled"; + }; + + wdt: watchdog@ff1a0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xff1a0000 0x0 0x100>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac: dmac@ff1f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff1f0000 0x0 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + }; + + saradc: saradc@ff280000 { + compatible = "rockchip,rk3328-saradc", "rockchip,saradc"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + cru: clock-controller@ff440000 { + compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; + reg = <0x0 0xff440000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = + <&cru DCLK_LCDC>, <&cru SCLK_PDM>, + <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, + <&cru SCLK_UART1>, <&cru SCLK_UART2>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, + <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, + <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, + <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, + <&cru SCLK_SDIO>, <&cru SCLK_TSP>, + <&cru SCLK_WIFI>, <&cru ARMCLK>, + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, + <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>, + <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>, + <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, + <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, + <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, + <&cru SCLK_EFUSE>, <&cru PCLK_DDR>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, + <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>; + assigned-clock-parents = + <&cru HDMIPHY>, <&cru PLL_APLL>, + <&cru PLL_GPLL>, <&xin24m>, + <&xin24m>, <&xin24m>; + assigned-clock-rates = + <0>, <61440000>, + <0>, <24000000>, + <24000000>, <24000000>, + <15000000>, <15000000>, + <100000000>, <100000000>, + <100000000>, <100000000>, + <50000000>, <100000000>, + <100000000>, <100000000>, + <50000000>, <50000000>, + <50000000>, <50000000>, + <24000000>, <600000000>, + <491520000>, <1200000000>, + <150000000>, <75000000>, + <75000000>, <150000000>, + <75000000>, <75000000>, + <300000000>, <100000000>, + <300000000>, <200000000>, + <400000000>, <500000000>, + <200000000>, <300000000>, + <300000000>, <250000000>, + <200000000>, <100000000>, + <24000000>, <100000000>, + <150000000>, <50000000>, + <32768>, <32768>; + }; + + sdmmc: rksdmmc@ff500000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff500000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdio: dwmmc@ff510000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff510000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + emmc: rksdmmc@ff520000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff520000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdmmc_ext: rksdmmc@ff5f0000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff5f0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + gic: interrupt-controller@ffb70000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xff811000 0 0x1000>, + <0x0 0xff812000 0 0x2000>, + <0x0 0xff814000 0 0x2000>, + <0x0 0xff816000 0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3328-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@ff210000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff210000 0x0 0x100>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@ff220000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff220000 0x0 0x100>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@ff230000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff230000 0x0 0x100>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@ff240000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff240000 0x0 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_2ma: pcfg-pull-none-2ma { + bias-disable; + drive-strength = <2>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_up_4ma: pcfg-pull-up-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_pull_none_4ma: pcfg-pull-none-4ma { + bias-disable; + drive-strength = <4>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_none_8ma: pcfg-pull-none-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + pcfg_pull_up_12ma: pcfg-pull-up-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + pcfg_input: pcfg-input { + input-enable; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + <2 24 RK_FUNC_1 &pcfg_pull_none>, + <2 25 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + <2 4 RK_FUNC_2 &pcfg_pull_none>, + <2 5 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = + <2 13 RK_FUNC_1 &pcfg_pull_none>, + <2 14 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = + <0 5 RK_FUNC_2 &pcfg_pull_none>, + <0 6 RK_FUNC_2 &pcfg_pull_none>; + }; + i2c3_gpio: i2c3-gpio { + rockchip,pins = + <0 5 RK_FUNC_GPIO &pcfg_pull_none>, + <0 6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi_i2c { + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = + <0 5 RK_FUNC_1 &pcfg_pull_none>, + <0 6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = + <1 9 RK_FUNC_1 &pcfg_pull_up>, + <1 8 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = + <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = + <1 10 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = + <1 10 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = + <3 4 RK_FUNC_4 &pcfg_pull_up>, + <3 6 RK_FUNC_4 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = + <3 7 RK_FUNC_4 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = + <3 5 RK_FUNC_4 &pcfg_pull_none>; + }; + + uart1_rts_gpio: uart1-rts-gpio { + rockchip,pins = + <3 5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart2-0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + <1 0 RK_FUNC_2 &pcfg_pull_up>, + <1 1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2-1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + <2 0 RK_FUNC_1 &pcfg_pull_up>, + <2 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spi0-0 { + spi0m0_clk: spi0m0-clk { + rockchip,pins = + <2 8 RK_FUNC_1 &pcfg_pull_up>; + }; + + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + <2 11 RK_FUNC_1 &pcfg_pull_up>; + }; + + spi0m0_tx: spi0m0-tx { + rockchip,pins = + <2 9 RK_FUNC_1 &pcfg_pull_up>; + }; + + spi0m0_rx: spi0m0-rx { + rockchip,pins = + <2 10 RK_FUNC_1 &pcfg_pull_up>; + }; + + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + <2 12 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi0-1 { + spi0m1_clk: spi0m1-clk { + rockchip,pins = + <3 23 RK_FUNC_2 &pcfg_pull_up>; + }; + + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + <3 26 RK_FUNC_2 &pcfg_pull_up>; + }; + + spi0m1_tx: spi0m1-tx { + rockchip,pins = + <3 25 RK_FUNC_2 &pcfg_pull_up>; + }; + + spi0m1_rx: spi0m1-rx { + rockchip,pins = + <3 24 RK_FUNC_2 &pcfg_pull_up>; + }; + + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins = + <3 27 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi0-2 { + spi0m2_clk: spi0m2-clk { + rockchip,pins = + <3 0 RK_FUNC_4 &pcfg_pull_up>; + }; + + spi0m2_cs0: spi0m2-cs0 { + rockchip,pins = + <3 8 RK_FUNC_3 &pcfg_pull_up>; + }; + + spi0m2_tx: spi0m2-tx { + rockchip,pins = + <3 1 RK_FUNC_4 &pcfg_pull_up>; + }; + + spi0m2_rx: spi0m2-rx { + rockchip,pins = + <3 2 RK_FUNC_4 &pcfg_pull_up>; + }; + }; + + i2s1 { + i2s1_mclk: i2s1-mclk { + rockchip,pins = + <2 15 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sclk: i2s1-sclk { + rockchip,pins = + <2 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_lrckrx: i2s1-lrckrx { + rockchip,pins = + <2 16 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_lrcktx: i2s1-lrcktx { + rockchip,pins = + <2 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sdi: i2s1-sdi { + rockchip,pins = + <2 19 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sdo: i2s1-sdo { + rockchip,pins = + <2 23 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sdio1: i2s1-sdio1 { + rockchip,pins = + <2 20 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sdio2: i2s1-sdio2 { + rockchip,pins = + <2 21 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sdio3: i2s1-sdio3 { + rockchip,pins = + <2 22 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s1_sleep: i2s1-sleep { + rockchip,pins = + <2 15 RK_FUNC_GPIO &pcfg_input_high>, + <2 16 RK_FUNC_GPIO &pcfg_input_high>, + <2 17 RK_FUNC_GPIO &pcfg_input_high>, + <2 18 RK_FUNC_GPIO &pcfg_input_high>, + <2 19 RK_FUNC_GPIO &pcfg_input_high>, + <2 20 RK_FUNC_GPIO &pcfg_input_high>, + <2 21 RK_FUNC_GPIO &pcfg_input_high>, + <2 22 RK_FUNC_GPIO &pcfg_input_high>, + <2 23 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + i2s2-0 { + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + <1 21 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + <1 22 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_lrckrx: i2s2m0-lrckrx { + rockchip,pins = + <1 26 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_lrcktx: i2s2m0-lrcktx { + rockchip,pins = + <1 23 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + <1 24 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + <1 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m0_sleep: i2s2m0-sleep { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_input_high>, + <1 22 RK_FUNC_GPIO &pcfg_input_high>, + <1 26 RK_FUNC_GPIO &pcfg_input_high>, + <1 23 RK_FUNC_GPIO &pcfg_input_high>, + <1 24 RK_FUNC_GPIO &pcfg_input_high>, + <1 25 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + i2s2-1 { + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + <1 21 RK_FUNC_1 &pcfg_pull_none>; + }; + + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + <3 0 RK_FUNC_6 &pcfg_pull_none>; + }; + + i2s2m1_lrckrx: i2sm1-lrckrx { + rockchip,pins = + <3 8 RK_FUNC_6 &pcfg_pull_none>; + }; + + i2s2m1_lrcktx: i2s2m1-lrcktx { + rockchip,pins = + <3 8 RK_FUNC_4 &pcfg_pull_none>; + }; + + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + <3 2 RK_FUNC_6 &pcfg_pull_none>; + }; + + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + <3 1 RK_FUNC_6 &pcfg_pull_none>; + }; + + i2s2m1_sleep: i2s2m1-sleep { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_input_high>, + <3 0 RK_FUNC_GPIO &pcfg_input_high>, + <3 8 RK_FUNC_GPIO &pcfg_input_high>, + <3 2 RK_FUNC_GPIO &pcfg_input_high>, + <3 1 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + spdif-0 { + spdifm0_tx: spdifm0-tx { + rockchip,pins = + <0 27 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spdif-1 { + spdifm1_tx: spdifm1-tx { + rockchip,pins = + <2 17 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + spdif-2 { + spdifm2_tx: spdifm2-tx { + rockchip,pins = + <0 2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + sdmmc0-0 { + sdmmc0m0_pwren: sdmmc0m0-pwren { + rockchip,pins = + <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0m0_gpio: sdmmc0m0-gpio { + rockchip,pins = + <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc0-1 { + sdmmc0m1_pwren: sdmmc0m1-pwren { + rockchip,pins = + <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0m1_gpio: sdmmc0m1-gpio { + rockchip,pins = + <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc0 { + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>; + }; + + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_dectn: sdmmc0-dectn { + rockchip,pins = + <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_wrprt: sdmmc0-wrprt { + rockchip,pins = + <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_bus1: sdmmc0-bus1 { + rockchip,pins = + <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>, + <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>, + <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>, + <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_gpio: sdmmc0-gpio { + rockchip,pins = + <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc0ext { + sdmmc0ext_clk: sdmmc0ext-clk { + rockchip,pins = + <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>; + }; + + sdmmc0ext_cmd: sdmmc0ext-cmd { + rockchip,pins = + <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_wrprt: sdmmc0ext-wrprt { + rockchip,pins = + <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_dectn: sdmmc0ext-dectn { + rockchip,pins = + <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_bus1: sdmmc0ext-bus1 { + rockchip,pins = + <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_bus4: sdmmc0ext-bus4 { + rockchip,pins = + <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>, + <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>, + <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>, + <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_gpio: sdmmc0ext-gpio { + rockchip,pins = + <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc1 { + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>; + }; + + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_wrprt: sdmmc1-wrprt { + rockchip,pins = + <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_dectn: sdmmc1-dectn { + rockchip,pins = + <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_bus1: sdmmc1-bus1 { + rockchip,pins = + <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>, + <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>, + <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>, + <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_gpio: sdmmc1-gpio { + rockchip,pins = + <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = + <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = + <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = + <3 22 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_rstnout: emmc-rstnout { + rockchip,pins = + <3 20 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = + <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = + <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = + <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>, + <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>, + <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>, + <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>, + <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = + <2 4 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = + <2 5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = + <2 6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwmir { + pwmir_pin: pwmir-pin { + rockchip,pins = + <2 2 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + gmac-0 { + rgmiim0_pins: rgmiim0-pins { + rockchip,pins = + /* mac_txclk */ + <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_rxclk */ + <0 10 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdio */ + <0 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_clk */ + <0 24 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxdv */ + <0 25 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ + <0 19 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd1 */ + <0 14 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd0 */ + <0 15 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_rxd3 */ + <0 20 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd2 */ + <0 21 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd3 */ + <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_txd2 */ + <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + + rmiim0_pins: rmiim0-pins { + rockchip,pins = + /* mac_mdio */ + <0 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_clk */ + <0 24 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxer */ + <0 13 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxdv */ + <0 25 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ + <0 19 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd1 */ + <0 14 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd0 */ + <0 15 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + }; + + gmac-1 { + rgmiim1_pins: rgmiim1-pins { + rockchip,pins = + /* mac_txclk */ + <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_rxclk */ + <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_mdio */ + <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_txen */ + <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_clk */ + <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxdv */ + <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_mdc */ + <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxd1 */ + <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxd0 */ + <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_txd1 */ + <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_rxd3 */ + <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxd2 */ + <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_txd3 */ + <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_txd2 */ + <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>, + + /* mac_txclk */ + <0 8 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <0 12 RK_FUNC_1 &pcfg_pull_none>, + /* mac_clk */ + <0 24 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 16 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd0 */ + <0 17 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd3 */ + <0 23 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd2 */ + <0 22 RK_FUNC_1 &pcfg_pull_none>; + }; + + rmiim1_pins: rmiim1-pins { + rockchip,pins = + /* mac_mdio */ + <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_txen */ + <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_clk */ + <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxer */ + <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxdv */ + <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_mdc */ + <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxd1 */ + <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_rxd0 */ + <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>, + /* mac_txd1 */ + <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>, + + /* mac_mdio */ + <0 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <0 12 RK_FUNC_1 &pcfg_pull_none>, + /* mac_clk */ + <0 24 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ + <0 19 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 16 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd0 */ + <0 17 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + gmac2phy { + fephyled_speed100: fephyled-speed100 { + rockchip,pins = + <0 31 RK_FUNC_1 &pcfg_pull_none>; + }; + + fephyled_speed10: fephyled-speed10 { + rockchip,pins = + <0 30 RK_FUNC_1 &pcfg_pull_none>; + }; + + fephyled_duplex: fephyled-duplex { + rockchip,pins = + <0 30 RK_FUNC_2 &pcfg_pull_none>; + }; + + fephyled_rxm0: fephyled-rxm0 { + rockchip,pins = + <0 29 RK_FUNC_1 &pcfg_pull_none>; + }; + + fephyled_txm0: fephyled-txm0 { + rockchip,pins = + <0 29 RK_FUNC_2 &pcfg_pull_none>; + }; + + fephyled_linkm0: fephyled-linkm0 { + rockchip,pins = + <0 28 RK_FUNC_1 &pcfg_pull_none>; + }; + + fephyled_rxm1: fephyled-rxm1 { + rockchip,pins = + <2 25 RK_FUNC_2 &pcfg_pull_none>; + }; + + fephyled_txm1: fephyled-txm1 { + rockchip,pins = + <2 25 RK_FUNC_3 &pcfg_pull_none>; + }; + + fephyled_linkm1: fephyled-linkm1 { + rockchip,pins = + <2 24 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + tsadc_pin { + tsadc_int: tsadc-int { + rockchip,pins = + <2 13 RK_FUNC_2 &pcfg_pull_none>; + }; + tsadc_gpio: tsadc-gpio { + rockchip,pins = + <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi_pin { + hdmi_cec: hdmi-cec { + rockchip,pins = + <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + + hdmi_hpd: hdmi-hpd { + rockchip,pins = + <0 4 RK_FUNC_1 &pcfg_pull_down>; + }; + }; + + cif-0 { + dvp_d2d9_m0:dvp-d2d9-m0 { + rockchip,pins = + /* cif_d0 */ + <3 4 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d1 */ + <3 5 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d2 */ + <3 6 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d3 */ + <3 7 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d4 */ + <3 8 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d5m0 */ + <3 9 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d6m0 */ + <3 10 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d7m0 */ + <3 11 RK_FUNC_2 &pcfg_pull_none>, + /* cif_href */ + <3 1 RK_FUNC_2 &pcfg_pull_none>, + /* cif_vsync */ + <3 0 RK_FUNC_2 &pcfg_pull_none>, + /* cif_clkoutm0 */ + <3 3 RK_FUNC_2 &pcfg_pull_none>, + /* cif_clkin */ + <3 2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + cif-1 { + dvp_d2d9_m1:dvp-d2d9-m1 { + rockchip,pins = + /* cif_d0 */ + <3 4 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d1 */ + <3 5 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d2 */ + <3 6 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d3 */ + <3 7 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d4 */ + <3 8 RK_FUNC_2 &pcfg_pull_none>, + /* cif_d5m1 */ + <2 16 RK_FUNC_4 &pcfg_pull_none>, + /* cif_d6m1 */ + <2 17 RK_FUNC_4 &pcfg_pull_none>, + /* cif_d7m1 */ + <2 18 RK_FUNC_4 &pcfg_pull_none>, + /* cif_href */ + <3 1 RK_FUNC_2 &pcfg_pull_none>, + /* cif_vsync */ + <3 0 RK_FUNC_2 &pcfg_pull_none>, + /* cif_clkoutm1 */ + <2 15 RK_FUNC_4 &pcfg_pull_none>, + /* cif_clkin */ + <3 2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + }; +}; |