ARM: AM33xx: Cleanup dplls data

Locking sequence for all the dplls is same.
In the current code same sequence is done repeatedly
for each dpll. Instead have a generic function
for locking dplls and pass dpll data to that function.

This is derived from OMAP4 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>

3 files changed, 73 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 44c1e5d..703b80e 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -13,4 +13,74 @@
 
 #include <asm/arch/clocks_am33xx.h>
 
+#define LDELAY 1000000
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+
+struct dpll_params {
+	u32 m;
+	u32 n;
+	s8 m2;
+	s8 m3;
+	s8 m4;
+	s8 m5;
+	s8 m6;
+};
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_dpll;
+	u32 cm_div_m5_dpll;
+	u32 cm_div_m6_dpll;
+};
+
+extern const struct dpll_regs dpll_mpu_regs;
+extern const struct dpll_regs dpll_core_regs;
+extern const struct dpll_regs dpll_per_regs;
+extern const struct dpll_regs dpll_ddr_regs;
+extern const struct dpll_params dpll_mpu;
+extern const struct dpll_params dpll_core;
+extern const struct dpll_params dpll_per;
+extern const struct dpll_params dpll_ddr;
+
+extern const struct cm_wkuppll *cmwkup;
+
+void setup_dplls(void);
+const struct dpll_params *get_dpll_ddr_params(void);
+void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
+
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 18d7d99..683ba8e 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -146,6 +146,8 @@ void set_sdram_timings(const struct emif_regs *regs, int nr);
  */
 void config_ddr_phy(const struct emif_regs *regs, int nr);
 
+void ddr_pll_config(unsigned int ddrpll_m);
+
 struct ddr_cmd_regs {
 	unsigned int resv0[7];
 	unsigned int cm0csratio;	/* offset 0x01C */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 1424f90..dbcede0 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -37,4 +37,5 @@ void omap_nand_switch_ecc(uint32_t, uint32_t);
 
 void rtc32k_enable(void);
 void uart_soft_reset(void);
+u32 wait_on_value(u32, u32, void *, u32);
 #endif