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| author | Rajesh Bhagat <rajesh.bhagat@nxp.com> | 2017-11-30 06:30:48 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2018-01-18 05:29:08 (GMT) |
| commit | fe1dc630a3e2fb4b845a1d612aff3c8160463c7d (patch) | |
| tree | fd4e7cdb03bf61faaca0b97504d072ab32556622 /arch/arm/include/asm/arch-fsl-layerscape/soc.h | |
| parent | 344badd84b079639ba51af9a5591df12fbe2cfa3 (diff) | |
| download | u-boot-fe1dc630a3e2fb4b845a1d612aff3c8160463c7d.tar.xz | |
armv8: lsch3: Add serdes and DDR voltage setup
Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/soc.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 0ff109d..66aa19b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -119,6 +119,7 @@ struct ccsr_ahci { #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); +int get_core_volt_from_fuse(void); #elif defined(CONFIG_FSL_LSCH2) void fsl_lsch2_early_init_f(void); int setup_chip_volt(void); |