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| author | York Sun <yorksun@freescale.com> | 2015-01-06 21:18:47 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 21:09:06 (GMT) |
| commit | 9955b4ab0187e0e9faac57acc01ebe7714d0ec23 (patch) | |
| tree | 0cf5592aeb45af97ff734a8653589dde5a16e1b7 /arch/arm/include/asm/arch-fsl-lsch3 | |
| parent | 1f3402e7291afa3ba0a5f4da72640edaf2f65405 (diff) | |
| download | u-boot-9955b4ab0187e0e9faac57acc01ebe7714d0ec23.tar.xz | |
driver/ddr/fsl: Add workaround for A008336
Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-lsch3')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/config.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index d4f688b..256adb0 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -30,6 +30,11 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL +#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL +#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL +#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL + #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) |