diff options
| author | Alison Wang <b18965@freescale.com> | 2014-12-09 09:38:14 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-12-11 17:40:24 (GMT) |
| commit | 8ab967b6c6007adbd30e58dfa9ef69154a351484 (patch) | |
| tree | 39d70fcc249733fe301bc156e06d29e55690ca60 /arch/arm/include/asm/arch-ls102xa | |
| parent | d612f0ab34b27be4ad50b1236fbd6c84450997f1 (diff) | |
| download | u-boot-8ab967b6c6007adbd30e58dfa9ef69154a351484.tar.xz | |
arm: ls102xa: Add NAND boot support for LS1021AQDS board
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-ls102xa')
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 |
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 704d683..ef775cf 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -15,6 +15,8 @@ #define CONFIG_SYS_IMMR 0x01000000 #define CONFIG_SYS_DCSRBAR 0x20000000 +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) + #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 98b268d..5abc3a1 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -29,6 +29,11 @@ #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define SYS_COUNTER_CTRL_ENABLE (1 << 24) +#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 +#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 + +#define DCFG_DCSR_PORCR1 0 + struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; |