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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-11 20:24:28 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-11 20:24:28 (GMT) |
| commit | cac423a730d3506154744485af1bbc1cd3a1e6a8 (patch) | |
| tree | 358b627972d9125de573c623f33e2da789f1de51 /arch/arm/include/asm/arch-omap5/clocks.h | |
| parent | c1b43ac7699640c8086bd73faa798bc9722d32c9 (diff) | |
| parent | 47c6ea076eb51e624f8744d93db5cd70b97dc25d (diff) | |
| download | u-boot-cac423a730d3506154744485af1bbc1cd3a1e6a8.tar.xz | |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/include/asm/arch-omap5/clocks.h')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/clocks.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index cfde374..68afa76 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -190,6 +190,10 @@ #define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 #define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) +/* PRM_RSTTIME */ +#define RSTTIME1_SHIFT 0 +#define RSTTIME1_MASK (0x3ff << 0) + /* Clock frequencies */ #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 @@ -251,4 +255,10 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 +/* + * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. + * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles + * into microsec and passing the value. + */ +#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 #endif /* _CLOCKS_OMAP5_H_ */ |