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| author | Stephen Warren <swarren@nvidia.com> | 2015-02-24 21:08:29 (GMT) |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-03-04 17:09:01 (GMT) |
| commit | 790f7719e2635a3ff3f44473b060e01b5b5ebf74 (patch) | |
| tree | a93d85ab77323e2d6536a324c3ee84c1ae2685ad /arch/arm/include/asm/arch-tegra114 | |
| parent | f2c60eed513ecc142e0a39373d5c16a14f976d6d (diff) | |
| download | u-boot-790f7719e2635a3ff3f44473b060e01b5b5ebf74.tar.xz | |
ARM: tegra: pinmux: account for different drivegroup base registers
Tegra210 starts its drive group registers at a different offset from the
APB MISC register block that other SoCs. Update the code to handle this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra114')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra114/pinmux.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 4848c95..38d8b9c 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -313,6 +313,7 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS #define TEGRA_PMX_GRPS_HAVE_LPMD |