diff options
author | Tom Warren <twarren.nvidia@gmail.com> | 2011-01-27 10:58:05 (GMT) |
---|---|---|
committer | Albert Aribaud <albert.aribaud@free.fr> | 2011-02-21 07:30:54 (GMT) |
commit | 3f82b1d3abf492038e14237f9c89bd55c31770ad (patch) | |
tree | 8bbff8ff342edace852b851f10d4e8d835bd8e96 /arch/arm/include/asm/arch-tegra2/tegra2.h | |
parent | 9b6442f99c617f147b95d9844a492c429e16e23c (diff) | |
download | u-boot-3f82b1d3abf492038e14237f9c89bd55c31770ad.tar.xz |
arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra2/tegra2.h')
-rw-r--r-- | arch/arm/include/asm/arch-tegra2/tegra2.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h new file mode 100644 index 0000000..9001b68 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA2_H_ +#define _TEGRA2_H_ + +#define NV_PA_SDRAM_BASE 0x00000000 +#define NV_PA_TMRUS_BASE 0x60005010 +#define NV_PA_CLK_RST_BASE 0x60006000 +#define NV_PA_APB_MISC_BASE 0x70000000 +#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) +#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) +#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) +#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) +#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) +#define NV_PA_PMC_BASE 0x7000E400 + +#define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE +#define LOW_LEVEL_SRAM_STACK 0x4000FFFC + +#ifndef __ASSEMBLY__ +struct timerus { + unsigned int cntr_1us; +}; +#else /* __ASSEMBLY__ */ +#define PRM_RSTCTRL NV_PA_PMC_BASE +#endif + +#endif /* TEGRA2_H */ |