Merge branch 'master' of git://git.denx.de/u-boot-arm

16 files changed, 157 insertions, 747 deletions

diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
new file mode 100644
index 0000000..a35940e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define MXC_CPU_MX51		0x51
+#define MXC_CPU_MX53		0x53
+#define MXC_CPU_MX6SL		0x60
+#define MXC_CPU_MX6DL		0x61
+#define MXC_CPU_MX6SOLO		0x62
+#define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6D		0x64
diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h
deleted file mode 100644
index c2e9c82..0000000
--- a/arch/arm/include/asm/arch-ixp/ixp425.h
+++ /dev/null
@@ -1,548 +0,0 @@
-/*
- * include/asm-arm/arch-ixp425/ixp425.h
- *
- * Register definitions for IXP425
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_ARM_IXP425_H_
-#define _ASM_ARM_IXP425_H_
-
-#define BIT(x)	(1<<(x))
-
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-#ifdef UBOOT_REG_FIX
-# undef	io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-#  define io_p2v(PhAdd)    (PhAdd)
-#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
-#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-#  define __REG(x) (x)
-# endif
-#endif /* UBOOT_REG_FIX */
-
-/*
- *
- * IXP425 Memory map:
- *
- * Phy		Phy Size	Map Size	Virt		Description
- * =========================================================================
- *
- * 0x00000000	0x10000000					SDRAM 1
- *
- * 0x10000000	0x10000000					SDRAM 2
- *
- * 0x20000000	0x10000000					SDRAM 3
- *
- * 0x30000000	0x10000000					SDRAM 4
- *
- * The above four are aliases to the same memory location  (0x00000000)
- *
- * 0x48000000	 0x4000000					PCI Memory
- *
- * 0x50000000	0x10000000			Not Mapped	EXP BUS
- *
- * 0x6000000	0x00004000	    0x4000	0xFFFEB000	QMgr
- *
- * 0xC0000000	     0x100	    0x1000	0xFFFDD000	PCI CFG
- *
- * 0xC4000000	     0x100          0x1000	0xFFFDE000	EXP CFG
- *
- * 0xC8000000	    0xC000          0xC000	0xFFFDF000	PERIPHERAL
- *
- * 0xCC000000	     0x100	    0x1000	Not Mapped	SDRAM CFG
- */
-
-/*
- * SDRAM
- */
-#define IXP425_SDRAM_BASE		(0x00000000)
-#define IXP425_SDRAM_BASE_ALT		(0x10000000)
-
-
-/*
- * PCI Configuration space
- */
-#define IXP425_PCI_CFG_BASE_PHYS	(0xC0000000)
-#define IXP425_PCI_CFG_REGION_SIZE	(0x00001000)
-
-/*
- * Expansion BUS Configuration registers
- */
-#define IXP425_EXP_CFG_BASE_PHYS	(0xC4000000)
-#define IXP425_EXP_CFG_REGION_SIZE	(0x00001000)
-
-/*
- * Peripheral space
- */
-#define IXP425_PERIPHERAL_BASE_PHYS	(0xC8000000)
-#define IXP425_PERIPHERAL_REGION_SIZE	(0x0000C000)
-
-/*
- * SDRAM configuration registers
- */
-#define IXP425_SDRAM_CFG_BASE_PHYS	(0xCC000000)
-
-/*
- * Q Manager space .. not static mapped
- */
-#define IXP425_QMGR_BASE_PHYS		(0x60000000)
-#define IXP425_QMGR_REGION_SIZE		(0x00004000)
-
-/*
- * Expansion BUS
- *
- * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
- * Exp Bus config registers:
- *
- * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
- * and The expansion bus to IXP425_EXP_BUS_BASE2
- */
-#define IXP425_EXP_BUS_BASE1_PHYS	(0x00000000)
-#define IXP425_EXP_BUS_BASE2_PHYS	(0x50000000)
-
-#define IXP425_EXP_BUS_BASE_PHYS	IXP425_EXP_BUS_BASE2_PHYS
-
-#define IXP425_EXP_BUS_REGION_SIZE	(0x08000000)
-#define IXP425_EXP_BUS_CSX_REGION_SIZE	(0x01000000)
-
-#define IXP425_EXP_BUS_CS0_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
-#define IXP425_EXP_BUS_CS1_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
-#define IXP425_EXP_BUS_CS2_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
-#define IXP425_EXP_BUS_CS3_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
-#define IXP425_EXP_BUS_CS4_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
-#define IXP425_EXP_BUS_CS5_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
-#define IXP425_EXP_BUS_CS6_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
-#define IXP425_EXP_BUS_CS7_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
-
-#define IXP425_FLASH_WRITABLE	(0x2)
-#define IXP425_FLASH_DEFAULT	(0xbcd23c40)
-#define IXP425_FLASH_WRITE	(0xbcd23c42)
-
-#define IXP425_EXP_CS0_OFFSET	0x00
-#define IXP425_EXP_CS1_OFFSET   0x04
-#define IXP425_EXP_CS2_OFFSET   0x08
-#define IXP425_EXP_CS3_OFFSET   0x0C
-#define IXP425_EXP_CS4_OFFSET   0x10
-#define IXP425_EXP_CS5_OFFSET   0x14
-#define IXP425_EXP_CS6_OFFSET   0x18
-#define IXP425_EXP_CS7_OFFSET   0x1C
-#define IXP425_EXP_CFG0_OFFSET	0x20
-#define IXP425_EXP_CFG1_OFFSET	0x24
-#define IXP425_EXP_CFG2_OFFSET	0x28
-#define IXP425_EXP_CFG3_OFFSET	0x2C
-
-/*
- * Expansion Bus Controller registers.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
-#else
-#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
-#endif
-
-#define IXP425_EXP_CS0      IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
-#define IXP425_EXP_CS1      IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
-#define IXP425_EXP_CS2      IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
-#define IXP425_EXP_CS3      IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
-#define IXP425_EXP_CS4      IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
-#define IXP425_EXP_CS5      IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
-#define IXP425_EXP_CS6      IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
-#define IXP425_EXP_CS7      IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
-
-#define IXP425_EXP_CFG0     IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
-#define IXP425_EXP_CFG1     IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
-#define IXP425_EXP_CFG2     IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
-#define IXP425_EXP_CFG3     IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
-
-/*
- * SDRAM Controller registers.
- */
-#define IXP425_SDR_CONFIG_OFFSET	0x00
-#define IXP425_SDR_REFRESH_OFFSET	0x04
-#define IXP425_SDR_IR_OFFSET		0x08
-
-#define IXP425_SDRAM_REG(x)	(IXP425_SDRAM_CFG_BASE_PHYS+(x))
-
-#define IXP425_SDR_CONFIG	IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
-#define IXP425_SDR_REFRESH	IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
-#define IXP425_SDR_IR		IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
-
-/*
- * UART registers
- */
-#define IXP425_UART1		0
-#define IXP425_UART2		0x1000
-
-#define IXP425_UART_RBR_OFFSET	0x00
-#define IXP425_UART_THR_OFFSET	0x00
-#define IXP425_UART_DLL_OFFSET	0x00
-#define IXP425_UART_IER_OFFSET	0x04
-#define IXP425_UART_DLH_OFFSET	0x04
-#define IXP425_UART_IIR_OFFSET	0x08
-#define IXP425_UART_FCR_OFFSET	0x00
-#define IXP425_UART_LCR_OFFSET	0x0c
-#define IXP425_UART_MCR_OFFSET	0x10
-#define IXP425_UART_LSR_OFFSET	0x14
-#define IXP425_UART_MSR_OFFSET	0x18
-#define IXP425_UART_SPR_OFFSET	0x1c
-#define IXP425_UART_ISR_OFFSET	0x20
-
-#define IXP425_UART_CFG_BASE_PHYS	(0xc8000000)
-
-#define RBR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
-#define THR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
-#define DLL(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
-#define IER(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
-#define DLH(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
-#define IIR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
-#define FCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
-#define LCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
-#define MCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
-#define LSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
-#define MSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
-#define SPR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
-#define ISR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
-
-#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
-#define IER_UUE		(1 << 6)	/* UART Unit Enable */
-#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
-#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
-#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
-#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
-#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
-#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
-#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
-#define IIR_TOD		(1 << 3)	/* Time Out Detected */
-#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
-#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
-#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
-
-#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
-#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
-#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
-#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
-#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1	(0)
-#define FCR_ITL_8	(FCR_ITL1)
-#define FCR_ITL_16	(FCR_ITL2)
-#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
-#define LCR_SB		(1 << 6)	/* Set Break */
-#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
-#define LCR_EPS		(1 << 4)	/* Even Parity Select */
-#define LCR_PEN		(1 << 3)	/* Parity Enable */
-#define LCR_STB		(1 << 2)	/* Stop Bit */
-#define LCR_WLS1	(1 << 1)	/* Word Length Select */
-#define LCR_WLS0	(1 << 0)	/* Word Length Select */
-
-#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
-#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
-#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
-#define LSR_BI		(1 << 4)	/* Break Interrupt */
-#define LSR_FE		(1 << 3)	/* Framing Error */
-#define LSR_PE		(1 << 2)	/* Parity Error */
-#define LSR_OE		(1 << 1)	/* Overrun Error */
-#define LSR_DR		(1 << 0)	/* Data Ready */
-
-#define MCR_LOOP	(1 << 4)	*/
-#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
-#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
-#define MCR_RTS		(1 << 1)	/* Request to Send */
-#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
-
-#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
-#define MSR_RI		(1 << 6)	/* Ring Indicator */
-#define MSR_DSR		(1 << 5)	/* Data Set Ready */
-#define MSR_CTS		(1 << 4)	/* Clear To Send */
-#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
-#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
-#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
-#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
-
-#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
-/*
- * Peripheral Space Registers
- */
-#define IXP425_UART1_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP425_UART2_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP425_PMU_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP425_INTC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP425_GPIO_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP425_TIMER_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP425_NPEA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP425_NPEB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP425_NPEC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
-#define IXP425_EthA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP425_EthB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP425_USB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
-
-/*
- * UART Register Definitions , Offsets only as there are 2 UARTS.
- *   IXP425_UART1_BASE , IXP425_UART2_BASE.
- */
-
-#undef  UART_NO_RX_INTERRUPT
-
-#define IXP425_UART_XTAL        14745600
-
-/*
- * Constants to make it easy to access  Interrupt Controller registers
- */
-#define IXP425_ICPR_OFFSET	0x00 /* Interrupt Status */
-#define IXP425_ICMR_OFFSET	0x04 /* Interrupt Enable */
-#define IXP425_ICLR_OFFSET	0x08 /* Interrupt IRQ/FIQ Select */
-#define IXP425_ICIP_OFFSET      0x0C /* IRQ Status */
-#define IXP425_ICFP_OFFSET	0x10 /* FIQ Status */
-#define IXP425_ICHR_OFFSET	0x14 /* Interrupt Priority */
-#define IXP425_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
-#define IXP425_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
-
-#define N_IRQS			32
-#define IXP425_TIMER_2_IRQ	11
-
-/*
- * Interrupt Controller Register Definitions.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
-#else
-#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
-#endif
-
-#define IXP425_ICPR     IXP425_INTC_REG(IXP425_ICPR_OFFSET)
-#define IXP425_ICMR     IXP425_INTC_REG(IXP425_ICMR_OFFSET)
-#define IXP425_ICLR     IXP425_INTC_REG(IXP425_ICLR_OFFSET)
-#define IXP425_ICIP     IXP425_INTC_REG(IXP425_ICIP_OFFSET)
-#define IXP425_ICFP     IXP425_INTC_REG(IXP425_ICFP_OFFSET)
-#define IXP425_ICHR     IXP425_INTC_REG(IXP425_ICHR_OFFSET)
-#define IXP425_ICIH     IXP425_INTC_REG(IXP425_ICIH_OFFSET)
-#define IXP425_ICFH     IXP425_INTC_REG(IXP425_ICFH_OFFSET)
-
-/*
- * Constants to make it easy to access GPIO registers
- */
-#define IXP425_GPIO_GPOUTR_OFFSET       0x00
-#define IXP425_GPIO_GPOER_OFFSET        0x04
-#define IXP425_GPIO_GPINR_OFFSET        0x08
-#define IXP425_GPIO_GPISR_OFFSET        0x0C
-#define IXP425_GPIO_GPIT1R_OFFSET	0x10
-#define IXP425_GPIO_GPIT2R_OFFSET	0x14
-#define IXP425_GPIO_GPCLKR_OFFSET	0x18
-#define IXP425_GPIO_GPDBSELR_OFFSET	0x1C
-
-/*
- * GPIO Register Definitions.
- * [Only perform 32bit reads/writes]
- */
-#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
-
-#define IXP425_GPIO_GPOUTR	IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
-#define IXP425_GPIO_GPOER       IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
-#define IXP425_GPIO_GPINR       IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
-#define IXP425_GPIO_GPISR       IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
-#define IXP425_GPIO_GPIT1R      IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
-#define IXP425_GPIO_GPIT2R      IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
-#define IXP425_GPIO_GPCLKR      IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
-#define IXP425_GPIO_GPDBSELR    IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
-
-#define IXP425_GPIO_GPITR(line)	(((line) >= 8) ? \
-				IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R)
-
-/*
- * Macros to make it easy to access the GPIO registers
- */
-#define GPIO_OUTPUT_ENABLE(line)	*IXP425_GPIO_GPOER &= ~(1 << (line))
-#define GPIO_OUTPUT_DISABLE(line)	*IXP425_GPIO_GPOER |= (1 << (line))
-#define GPIO_OUTPUT_SET(line)		*IXP425_GPIO_GPOUTR |= (1 << (line))
-#define GPIO_OUTPUT_CLEAR(line)		*IXP425_GPIO_GPOUTR &= ~(1 << (line))
-#define GPIO_INT_ACT_LOW_SET(line)				\
-	*IXP425_GPIO_GPITR(line) =				\
-			(*IXP425_GPIO_GPITR(line) &		\
-			~(0x7 << (((line) & 0x7) * 3))) |	\
-			(0x1 << (((line) & 0x7) * 3))		\
-
-/*
- * Constants to make it easy to access Timer Control/Status registers
- */
-#define IXP425_OSTS_OFFSET	0x00  /* Continious TimeStamp */
-#define IXP425_OST1_OFFSET	0x04  /* Timer 1 Timestamp */
-#define IXP425_OSRT1_OFFSET	0x08  /* Timer 1 Reload */
-#define IXP425_OST2_OFFSET	0x0C  /* Timer 2 Timestamp */
-#define IXP425_OSRT2_OFFSET	0x10  /* Timer 2 Reload */
-#define IXP425_OSWT_OFFSET	0x14  /* Watchdog Timer */
-#define IXP425_OSWE_OFFSET	0x18  /* Watchdog Enable */
-#define IXP425_OSWK_OFFSET	0x1C  /* Watchdog Key */
-#define IXP425_OSST_OFFSET	0x20  /* Timer Status */
-
-/*
- * Operating System Timer Register Definitions.
- */
-
-#ifndef __ASSEMBLY__
-#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
-#else
-#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
-#endif
-
-/* _B to avoid collision: also defined in npe/include/... */
-#define IXP425_OSTS_B	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
-#define IXP425_OST1	IXP425_TIMER_REG(IXP425_OST1_OFFSET)
-#define IXP425_OSRT1	IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
-#define IXP425_OST2	IXP425_TIMER_REG(IXP425_OST2_OFFSET)
-#define IXP425_OSRT2	IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
-#define IXP425_OSWT	IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
-#define IXP425_OSWE	IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
-#define IXP425_OSWK	IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
-#define IXP425_OSST	IXP425_TIMER_REG(IXP425_OSST_OFFSET)
-
-/*
- * Timer register values and bit definitions
- */
-#define IXP425_OST_ENABLE              BIT(0)
-#define IXP425_OST_ONE_SHOT            BIT(1)
-/* Low order bits of reload value ignored */
-#define IXP425_OST_RELOAD_MASK         (0x3)
-#define IXP425_OST_DISABLED            (0x0)
-#define IXP425_OSST_TIMER_1_PEND       BIT(0)
-#define IXP425_OSST_TIMER_2_PEND       BIT(1)
-#define IXP425_OSST_TIMER_TS_PEND      BIT(2)
-#define IXP425_OSST_TIMER_WDOG_PEND    BIT(3)
-#define IXP425_OSST_TIMER_WARM_RESET   BIT(4)
-
-/*
- * Constants to make it easy to access PCI Control/Status registers
- */
-#define PCI_NP_AD_OFFSET            0x00
-#define PCI_NP_CBE_OFFSET           0x04
-#define PCI_NP_WDATA_OFFSET         0x08
-#define PCI_NP_RDATA_OFFSET         0x0c
-#define PCI_CRP_AD_CBE_OFFSET       0x10
-#define PCI_CRP_WDATA_OFFSET        0x14
-#define PCI_CRP_RDATA_OFFSET        0x18
-#define PCI_CSR_OFFSET              0x1c
-#define PCI_ISR_OFFSET              0x20
-#define PCI_INTEN_OFFSET            0x24
-#define PCI_DMACTRL_OFFSET          0x28
-#define PCI_AHBMEMBASE_OFFSET       0x2c
-#define PCI_AHBIOBASE_OFFSET        0x30
-#define PCI_PCIMEMBASE_OFFSET       0x34
-#define PCI_AHBDOORBELL_OFFSET      0x38
-#define PCI_PCIDOORBELL_OFFSET      0x3C
-#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
-#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
-#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
-#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
-#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
-#define PCI_ATPDMA1_LENADDR_OFFSET  0x54
-
-/*
- * PCI Control/Status Registers
- */
-#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
-
-#define PCI_NP_AD               IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
-#define PCI_NP_CBE              IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
-#define PCI_NP_WDATA            IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
-#define PCI_NP_RDATA            IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
-#define PCI_CRP_AD_CBE          IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
-#define PCI_CRP_WDATA           IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
-#define PCI_CRP_RDATA           IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
-#define PCI_CSR                 IXP425_PCI_CSR(PCI_CSR_OFFSET)
-#define PCI_ISR                 IXP425_PCI_CSR(PCI_ISR_OFFSET)
-#define PCI_INTEN               IXP425_PCI_CSR(PCI_INTEN_OFFSET)
-#define PCI_DMACTRL             IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
-#define PCI_AHBMEMBASE          IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
-#define PCI_AHBIOBASE           IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
-#define PCI_PCIMEMBASE          IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
-#define PCI_AHBDOORBELL         IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
-#define PCI_PCIDOORBELL         IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
-#define PCI_ATPDMA0_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
-#define PCI_ATPDMA0_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
-#define PCI_ATPDMA0_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
-#define PCI_ATPDMA1_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
-#define PCI_ATPDMA1_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
-#define PCI_ATPDMA1_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
-
-/*
- * PCI register values and bit definitions
- */
-
-/* CSR bit definitions */
-#define PCI_CSR_HOST		BIT(0)
-#define PCI_CSR_ARBEN		BIT(1)
-#define PCI_CSR_ADS		BIT(2)
-#define PCI_CSR_PDS		BIT(3)
-#define PCI_CSR_ABE		BIT(4)
-#define PCI_CSR_DBT		BIT(5)
-#define PCI_CSR_ASE		BIT(8)
-#define PCI_CSR_IC		BIT(15)
-
-/* ISR (Interrupt status) Register bit definitions */
-#define PCI_ISR_PSE		BIT(0)
-#define PCI_ISR_PFE		BIT(1)
-#define PCI_ISR_PPE		BIT(2)
-#define PCI_ISR_AHBE		BIT(3)
-#define PCI_ISR_APDC		BIT(4)
-#define PCI_ISR_PADC		BIT(5)
-#define PCI_ISR_ADB		BIT(6)
-#define PCI_ISR_PDB		BIT(7)
-
-/* INTEN (Interrupt Enable) Register bit definitions */
-#define PCI_INTEN_PSE		BIT(0)
-#define PCI_INTEN_PFE		BIT(1)
-#define PCI_INTEN_PPE		BIT(2)
-#define PCI_INTEN_AHBE		BIT(3)
-#define PCI_INTEN_APDC		BIT(4)
-#define PCI_INTEN_PADC		BIT(5)
-#define PCI_INTEN_ADB		BIT(6)
-#define PCI_INTEN_PDB		BIT(7)
-
-/*
- * Shift value for byte enable on NP cmd/byte enable register
- */
-#define IXP425_PCI_NP_CBE_BESL	4
-
-/*
- * PCI commands supported by NP access unit
- */
-#define NP_CMD_IOREAD		0x2
-#define NP_CMD_IOWRITE		0x3
-#define NP_CMD_CONFIGREAD	0xa
-#define NP_CMD_CONFIGWRITE	0xb
-#define NP_CMD_MEMREAD		0x6
-#define	NP_CMD_MEMWRITE		0x7
-
-#if 0
-#ifndef __ASSEMBLY__
-extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
-extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
-extern void ixp425_pci_init(void *);
-#endif
-#endif
-
-/*
- * Constants for CRP access into local config space
- */
-#define CRP_AD_CBE_BESL         20
-#define CRP_AD_CBE_WRITE        BIT(16)
-
-/*
- * Clock Speed Definitions.
- */
-#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS   */
-
-
-#endif
diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h
deleted file mode 100644
index f499883..0000000
--- a/arch/arm/include/asm/arch-ixp/ixp425pci.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * IXP PCI Init
- * (C) Copyright 2004 eslab.whut.edu.cn
- * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _IXP425PCI_H
-#define _IXP425PCI_H
-
-#define OK	0
-#define ERROR	-1
-
-struct pci_controller;
-extern void pci_ixp_init(struct pci_controller *hose);
-
-/* Mask definitions*/
-#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK	0x0000000f
-
-#define PCI_NP_CBE_BESL	 (4)
-#define PCI_NP_AD_FUNCSL (8)
-
-/*Register addressing definitions for PCI controller configuration
-  and status registers*/
-
-#define PCI_CSR_BASE (0xC0000000)
-/*
-#define PCI_NP_AD_OFFSET       (0x00)
-#define PCI_NP_CBE_OFFSET      (0x04)
-#define PCI_NP_WDATA_OFFSET    (0x08)
-#define PCI_NP_RDATA_OFFSET    (0x0C)
-#define PCI_CRP_OFFSET	       (0x10)
-#define PCI_CRP_WDATA_OFFSET   (0x14)
-#define PCI_CRP_RDATA_OFFSET   (0x18)
-#define PCI_CSR_OFFSET	       (0x1C)
-#define PCI_ISR_OFFSET	       (0x20)
-#define PCI_INTEN_OFFSET       (0x24)
-#define PCI_DMACTRL_OFFSET     (0x28)
-#define PCI_AHBMEMBASE_OFFSET  (0x2C)
-#define PCI_AHBIOBASE_OFFSET   (0x30)
-#define PCI_PCIMEMBASE_OFFSET  (0x34)
-#define PCI_AHBDOORBELL_OFFSET (0x38)
-#define PCI_PCIDOORBELL_OFFSET (0x3C)
-#define PCI_ATPDMA0_AHBADDR    (0x40)
-#define PCI_ATPDMA0_PCIADDR    (0x44)
-#define PCI_ATPDMA0_LENADDR    (0x48)
-#define PCI_ATPDMA1_AHBADDR    (0x4C)
-#define PCI_ATPDMA1_PCIADDR    (0x50)
-#define PCI_ATPDMA1_LENADDR    (0x54)
-#define PCI_PTADMA0_AHBADDR    (0x58)
-#define PCI_PTADMA0_PCIADDR    (0x5C)
-#define PCI_PTADMA0_LENADDR    (0x60)
-#define PCI_PTADMA1_AHBADDR    (0x64)
-#define PCI_PTADMA1_PCIADDR    (0x68)
-#define PCI_PTADMA1_LENADDR    (0x6C)
-*/
-/*Non prefetch registers bit definitions*/
-/*
-#define NP_CMD_INTACK	   (0x0)
-#define NP_CMD_SPECIAL	   (0x1)
-#define NP_CMD_IOREAD	   (0x2)
-#define NP_CMD_IOWRITE	   (0x3)
-#define NP_CMD_MEMREAD	   (0x6)
-#define NP_CMD_MEMWRITE	   (0x7)
-#define NP_CMD_CONFIGREAD  (0xa)
-#define NP_CMD_CONFIGWRITE (0xb)
-*/
-
-/*Configuration Port register bit definitions*/
-#define PCI_CRP_WRITE BIT(16)
-
-/*ISR (Interrupt status) Register bit definitions*/
-#define PCI_ISR_PSE   BIT(0)
-#define PCI_ISR_PFE   BIT(1)
-#define PCI_ISR_PPE   BIT(2)
-#define PCI_ISR_AHBE  BIT(3)
-#define PCI_ISR_APDC  BIT(4)
-#define PCI_ISR_PADC  BIT(5)
-#define PCI_ISR_ADB   BIT(6)
-#define PCI_ISR_PDB   BIT(7)
-
-/*INTEN (Interrupt Enable) Register bit definitions*/
-#define PCI_INTEN_PSE	BIT(0)
-#define PCI_INTEN_PFE	BIT(1)
-#define PCI_INTEN_PPE	BIT(2)
-#define PCI_INTEN_AHBE	BIT(3)
-#define PCI_INTEN_APDC	BIT(4)
-#define PCI_INTEN_PADC	BIT(5)
-#define PCI_INTEN_ADB	BIT(6)
-#define PCI_INTEN_PDB	BIT(7)
-
-/*PCI configuration regs.*/
-
-#define PCI_CFG_VENDOR_ID	0x00
-#define PCI_CFG_DEVICE_ID	0x02
-#define PCI_CFG_COMMAND		0x04
-#define PCI_CFG_STATUS		0x06
-#define PCI_CFG_REVISION	0x08
-#define PCI_CFG_PROGRAMMING_IF	0x09
-#define PCI_CFG_SUBCLASS	0x0a
-#define PCI_CFG_CLASS		0x0b
-#define PCI_CFG_CACHE_LINE_SIZE 0x0c
-#define PCI_CFG_LATENCY_TIMER	0x0d
-#define PCI_CFG_HEADER_TYPE	0x0e
-#define PCI_CFG_BIST		0x0f
-#define PCI_CFG_BASE_ADDRESS_0	0x10
-#define PCI_CFG_BASE_ADDRESS_1	0x14
-#define PCI_CFG_BASE_ADDRESS_2	0x18
-#define PCI_CFG_BASE_ADDRESS_3	0x1c
-#define PCI_CFG_BASE_ADDRESS_4	0x20
-#define PCI_CFG_BASE_ADDRESS_5	0x24
-#define PCI_CFG_CIS		0x28
-#define PCI_CFG_SUB_VENDOR_ID	0x2c
-#define PCI_CFG_SUB_SYSTEM_ID	0x2e
-#define PCI_CFG_EXPANSION_ROM	0x30
-#define PCI_CFG_RESERVED_0	0x34
-#define PCI_CFG_RESERVED_1	0x38
-#define PCI_CFG_DEV_INT_LINE	0x3c
-#define PCI_CFG_DEV_INT_PIN	0x3d
-#define PCI_CFG_MIN_GRANT	0x3e
-#define PCI_CFG_MAX_LATENCY	0x3f
-#define PCI_CFG_SPECIAL_USE	0x41
-#define PCI_CFG_MODE		0x43
-
-#define PCI_CMD_IO_ENABLE	0x0001	/* IO access enable */
-#define PCI_CMD_MEM_ENABLE	0x0002	/* memory access enable */
-#define PCI_CMD_MASTER_ENABLE	0x0004	/* bus master enable */
-#define PCI_CMD_MON_ENABLE	0x0008	/* monitor special cycles enable */
-#define PCI_CMD_WI_ENABLE	0x0010	/* write and invalidate enable */
-#define PCI_CMD_SNOOP_ENABLE	0x0020	/* palette snoop enable */
-#define PCI_CMD_PERR_ENABLE	0x0040	/* parity error enable */
-#define PCI_CMD_WC_ENABLE	0x0080	/* wait cycle enable */
-#define PCI_CMD_SERR_ENABLE	0x0100	/* system error enable */
-#define PCI_CMD_FBTB_ENABLE	0x0200	/* fast back to back enable */
-
-
-/*CSR Register bit definitions*/
-#define PCI_CSR_HOST  BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS   BIT(2)
-#define PCI_CSR_PDS   BIT(3)
-#define PCI_CSR_ABE   BIT(4)
-#define PCI_CSR_DBT   BIT(5)
-#define PCI_CSR_ASE   BIT(8)
-#define PCI_CSR_IC    BIT(15)
-
-/*Configuration command bit definitions*/
-#define PCI_CFG_CMD_IOAE BIT(0)
-#define PCI_CFG_CMD_MAE	 BIT(1)
-#define PCI_CFG_CMD_BME	 BIT(2)
-#define PCI_CFG_CMD_MWIE BIT(4)
-#define PCI_CFG_CMD_SER	 BIT(8)
-#define PCI_CFG_CMD_FBBE BIT(9)
-#define PCI_CFG_CMD_MDPE BIT(24)
-#define PCI_CFG_CMD_STA	 BIT(27)
-#define PCI_CFG_CMD_RTA	 BIT(28)
-#define PCI_CFG_CMD_RMA	 BIT(29)
-#define PCI_CFG_CMD_SSE	 BIT(30)
-#define PCI_CFG_CMD_DPE	 BIT(31)
-
-/*DMACTRL DMA Control and status Register*/
-#define PCI_DMACTRL_APDCEN  BIT(0)
-#define PCI_DMACTRL_APDC0   BIT(4)
-#define PCI_DMACTRL_APDE0   BIT(5)
-#define PCI_DMACTRL_APDC1   BIT(6)
-#define PCI_DMACTRL_APDE1   BIT(7)
-#define PCI_DMACTRL_PADCEN  BIT(8)
-#define PCI_DMACTRL_PADC0   BIT(12)
-#define PCI_DMACTRL_PADE0   BIT(13)
-#define PCI_DMACTRL_PADC1   BIT(14)
-#define PCI_DMACTRL_PADE1   BIT(15)
-
-#endif
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index 9949ad1..ac7705b 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -8,12 +8,7 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-#define MXC_CPU_MX51		0x51
-#define MXC_CPU_MX53		0x53
-#define MXC_CPU_MX6SL		0x60
-#define MXC_CPU_MX6DL		0x61
-#define MXC_CPU_MX6SOLO		0x62
-#define MXC_CPU_MX6Q		0x63
+#include "../arch-imx/cpu.h"
 
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index e31ba0a..1b4ded7 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -55,6 +55,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk);
 void enable_ocotp_clk(unsigned char enable);
 void enable_usboh3_clk(unsigned char enable);
 int enable_sata_clock(void);
+int enable_pcie_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index f2ad6e9..c2d210a 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -53,6 +53,7 @@
 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
+#define L2_PL310_BASE			0x00A02000
 #define GPV0_BASE_ADDR                  0x00B00000
 #define GPV1_BASE_ADDR                  0x00C00000
 #define PCIE_ARB_BASE_ADDR              0x01000000
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index fe4675e..f9ee0d9 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -15,6 +15,33 @@
 #define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR	(0<<13)
 #define IOMUXC_GPR1_OTG_ID_GPIO1	(1<<13)
 #define IOMUXC_GPR1_OTG_ID_MASK		(1<<13)
+#define IOMUXC_GPR1_REF_SSP_EN			(1 << 16)
+#define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
+
+/*
+ * IOMUXC_GPR8 bit fields
+ */
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK		(0x3f << 0)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET		0
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK	(0x3f << 6)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET	6
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK		(0x3f << 12)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET	12
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK		(0x7f << 18)
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET		18
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK		(0x7f << 25)
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET		25
+
+/*
+ * IOMUXC_GPR12 bit fields
+ */
+#define IOMUXC_GPR12_LOS_LEVEL_9		(0x9 << 4)
+#define IOMUXC_GPR12_LOS_LEVEL_MASK		(0x1f << 4)
+#define IOMUXC_GPR12_APPS_LTSSM_ENABLE		(1 << 10)
+#define IOMUXC_GPR12_DEVICE_TYPE_EP		(0x0 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x2 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_MASK		(0xf << 12)
+
 /*
  * IOMUXC_GPR13 bit fields
  */
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 55cc9ad..2e414ad 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -647,7 +647,7 @@ MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK,	0x05BC, 0x01EC, 2, 0x083C, 0, 0)
 MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT,	0x05BC, 0x01EC, 4, 0x0000, 0, 0)
 MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22,	0x05BC, 0x01EC, 5, 0x0000, 0, 0)
 MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK,	0x05BC, 0x01EC, 6, 0x0000, 0, 0)
-MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK,	0x05C0, 0x01F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK,	0x05C0, 0x01F0, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
 MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS,	0x05C0, 0x01F0, 2, 0x082C, 0, 0)
 MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23,	0x05C0, 0x01F0, 5, 0x0000, 0, 0)
 MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK,	0x05C0, 0x01F0, 6, 0x0000, 0, 0)
@@ -695,7 +695,7 @@ MX6_PAD_DECL(GPIO_1__GPIO1_IO01,	0x05E0, 0x0210, 5, 0x0000, 0, 0)
 MX6_PAD_DECL(GPIO_1__SD1_CD_B,	0x05E0, 0x0210, 6, 0x0000, 0, 0)
 MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,	0x05E4, 0x0214, 0, 0x0850, 1, 0)
 MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN,	0x05E4, 0x0214, 1, 0x0000, 0, 0)
-MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,	0x05E4, 0x0214, 2, 0x080C, 0, 0)
+MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,	0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0)
 MX6_PAD_DECL(GPIO_16__SD1_LCTL,	0x05E4, 0x0214, 3, 0x0000, 0, 0)
 MX6_PAD_DECL(GPIO_16__SPDIF_IN,	0x05E4, 0x0214, 4, 0x08F0, 2, 0)
 MX6_PAD_DECL(GPIO_16__GPIO7_IO11,	0x05E4, 0x0214, 5, 0x0000, 0, 0)
@@ -934,7 +934,7 @@ MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE,	0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SI
 MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE,	0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP)
 MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL,	0x06BC, 0x02D4, 1, 0x0000, 0, 0)
 MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26,	0x06BC, 0x02D4, 5, 0x0000, 0, 0)
-MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK,	0x06BC, 0x02D4, 7, 0x080C, 1, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK,	0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0)
 MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA,	0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
 MX6_PAD_DECL(RGMII_TXC__RGMII_TXC,	0x06C0, 0x02D8, 1, 0x0000, 0, 0)
 MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK,	0x06C0, 0x02D8, 2, 0x08F4, 1, 0)
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index ad31c33..a8456a2 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -53,7 +53,7 @@ MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25,	0x0384, 0x0070, 5, 0x0000, 0, 0)
 MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE,	0x0388, 0x0074, 0, 0x0000, 0, 0)
 MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL,	0x0388, 0x0074, 1, 0x0000, 0, 0)
 MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26,	0x0388, 0x0074, 5, 0x0000, 0, 0)
-MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK,	0x0388, 0x0074, 7, 0x083C, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK,	0x0388, 0x0074, 7 | IOMUX_CONFIG_SION, 0x083C, 0, 0)
 MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG,	0x038C, 0x0078, 0, 0x0000, 0, 0)
 MX6_PAD_DECL(RGMII_RD1__RGMII_RD1,	0x038C, 0x0078, 1, 0x084C, 0, 0)
 MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27,	0x038C, 0x0078, 5, 0x0000, 0, 0)
@@ -523,7 +523,7 @@ MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK,	0x04E4, 0x01D0, 2, 0x086C, 0, 0)
 MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT,	0x04E4, 0x01D0, 4, 0x0000, 0, 0)
 MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22,	0x04E4, 0x01D0, 5, 0x0000, 0, 0)
 MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK,	0x04E4, 0x01D0, 6, 0x0000, 0, 0)
-MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK,	0x04E8, 0x01D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK,	0x04E8, 0x01D4, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
 MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS,	0x04E8, 0x01D4, 2, 0x085C, 0, 0)
 MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23,	0x04E8, 0x01D4, 5, 0x0000, 0, 0)
 MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK,	0x04E8, 0x01D4, 6, 0x0000, 0, 0)
@@ -703,7 +703,7 @@ MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK,	0x0614, 0x0244, 6, 0x0000, 0, 0)
 MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE,	0x0614, 0x0244, 7, 0x0000, 0, 0)
 MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,	0x0618, 0x0248, 0, 0x0880, 1, 0)
 MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN,	0x0618, 0x0248, 1, 0x0000, 0, 0)
-MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,	0x0618, 0x0248, 2, 0x083C, 1, 0)
+MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,	0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0)
 MX6_PAD_DECL(GPIO_16__SD1_LCTL,	0x0618, 0x0248, 3, 0x0000, 0, 0)
 MX6_PAD_DECL(GPIO_16__SPDIF_IN,	0x0618, 0x0248, 4, 0x0914, 3, 0)
 MX6_PAD_DECL(GPIO_16__GPIO7_IO11,	0x0618, 0x0248, 5, 0x0000, 0, 0)
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 17125a6..38851a1 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -9,13 +9,7 @@
 #define _SYS_PROTO_H_
 
 #include <asm/imx-common/regs-common.h>
-
-#define MXC_CPU_MX51		0x51
-#define MXC_CPU_MX53		0x53
-#define MXC_CPU_MX6SL		0x60
-#define MXC_CPU_MX6DL		0x61
-#define MXC_CPU_MX6SOLO		0x62
-#define MXC_CPU_MX6Q		0x63
+#include "../arch-imx/cpu.h"
 
 #define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
diff --git a/arch/arm/include/asm/arch-zynq/clk.h b/arch/arm/include/asm/arch-zynq/clk.h
new file mode 100644
index 0000000..250c5bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/clk.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ZYNQ_CLK_H_
+#define _ZYNQ_CLK_H_
+
+enum zynq_clk {
+	armpll_clk, ddrpll_clk, iopll_clk,
+	cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
+	ddr2x_clk, ddr3x_clk, dci_clk,
+	lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
+	fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
+	sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
+	usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
+	sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
+	can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
+	uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
+	smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
+
+void zynq_clk_early_init(void);
+int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate);
+unsigned long zynq_clk_get_rate(enum zynq_clk clk);
+const char *zynq_clk_get_name(enum zynq_clk clk);
+unsigned long get_uart_clk(int dev_id);
+
+#endif
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index cd69677..39184da 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -7,6 +7,8 @@
 #ifndef _ASM_ARCH_HARDWARE_H
 #define _ASM_ARCH_HARDWARE_H
 
+#define ZYNQ_SERIAL_BASEADDR0		0xE0000000
+#define ZYNQ_SERIAL_BASEADDR1		0xE0001000
 #define ZYNQ_SYS_CTRL_BASEADDR		0xF8000000
 #define ZYNQ_DEV_CFG_APB_BASEADDR	0xF8007000
 #define ZYNQ_SCU_BASEADDR		0xF8F00000
@@ -21,17 +23,51 @@
 #define ZYNQ_SPI_BASEADDR1		0xE0007000
 #define ZYNQ_DDRC_BASEADDR		0xF8006000
 
+/* Bootmode setting values */
+#define ZYNQ_BM_MASK		0xF
+#define ZYNQ_BM_NOR		0x2
+#define ZYNQ_BM_SD		0x5
+#define ZYNQ_BM_JTAG		0x0
+
 /* Reflect slcr offsets */
 struct slcr_regs {
 	u32 scl; /* 0x0 */
 	u32 slcr_lock; /* 0x4 */
 	u32 slcr_unlock; /* 0x8 */
-	u32 reserved0[75];
+	u32 reserved0_1[61];
+	u32 arm_pll_ctrl; /* 0x100 */
+	u32 ddr_pll_ctrl; /* 0x104 */
+	u32 io_pll_ctrl; /* 0x108 */
+	u32 reserved0_2[5];
+	u32 arm_clk_ctrl; /* 0x120 */
+	u32 ddr_clk_ctrl; /* 0x124 */
+	u32 dci_clk_ctrl; /* 0x128 */
+	u32 aper_clk_ctrl; /* 0x12c */
+	u32 reserved0_3[2];
 	u32 gem0_rclk_ctrl; /* 0x138 */
 	u32 gem1_rclk_ctrl; /* 0x13c */
 	u32 gem0_clk_ctrl; /* 0x140 */
 	u32 gem1_clk_ctrl; /* 0x144 */
-	u32 reserved1[46];
+	u32 smc_clk_ctrl; /* 0x148 */
+	u32 lqspi_clk_ctrl; /* 0x14c */
+	u32 sdio_clk_ctrl; /* 0x150 */
+	u32 uart_clk_ctrl; /* 0x154 */
+	u32 spi_clk_ctrl; /* 0x158 */
+	u32 can_clk_ctrl; /* 0x15c */
+	u32 can_mioclk_ctrl; /* 0x160 */
+	u32 dbg_clk_ctrl; /* 0x164 */
+	u32 pcap_clk_ctrl; /* 0x168 */
+	u32 reserved0_4[1];
+	u32 fpga0_clk_ctrl; /* 0x170 */
+	u32 reserved0_5[3];
+	u32 fpga1_clk_ctrl; /* 0x180 */
+	u32 reserved0_6[3];
+	u32 fpga2_clk_ctrl; /* 0x190 */
+	u32 reserved0_7[3];
+	u32 fpga3_clk_ctrl; /* 0x1a0 */
+	u32 reserved0_8[8];
+	u32 clk_621_true; /* 0x1c4 */
+	u32 reserved1[14];
 	u32 pss_rst_ctrl; /* 0x200 */
 	u32 reserved2[15];
 	u32 fpga_rst_ctrl; /* 0x240 */
diff --git a/arch/arm/include/asm/arch-zynq/spl.h b/arch/arm/include/asm/arch-zynq/spl.h
new file mode 100644
index 0000000..5789d28
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynq/spl.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+extern void ps7_init(void);
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_RAM		1
+#define BOOT_DEVICE_SPI		2
+#define BOOT_DEVICE_MMC1	3
+#define BOOT_DEVICE_MMC2	4
+#define BOOT_DEVICE_MMC2_2	5
+
+#endif
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 8f925af..0a2ba05 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -10,7 +10,7 @@
 extern void zynq_slcr_lock(void);
 extern void zynq_slcr_unlock(void);
 extern void zynq_slcr_cpu_reset(void);
-extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
 extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
 extern u32 zynq_slcr_get_boot_mode(void);
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 60e8726..63e4ad5 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -32,9 +32,6 @@ struct arch_global_data {
 	unsigned long tbl;
 	unsigned long lastinc;
 	unsigned long long timer_reset_value;
-#ifdef CONFIG_IXP425
-	unsigned long timestamp;
-#endif
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	unsigned long tlb_addr;
 	unsigned long tlb_size;
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index f41ad8c..ddc245b 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -12,6 +12,9 @@
 
 /* Register bit fields */
 #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK	(1 << 16)
+#define L2X0_DYNAMIC_CLK_GATING_EN		(1 << 1)
+#define L2X0_STNDBY_MODE_EN			(1 << 0)
+#define L2X0_CTRL_EN				1
 
 struct pl310_regs {
 	u32 pl310_cache_id;
@@ -47,6 +50,24 @@ struct pl310_regs {
 	u32 pad9[1];
 	u32 pl310_clean_inv_line_idx;
 	u32 pl310_clean_inv_way;
+	u32 pad10[64];
+	u32 pl310_lockdown_dbase;
+	u32 pl310_lockdown_ibase;
+	u32 pad11[190];
+	u32 pl310_addr_filter_start;
+	u32 pl310_addr_filter_end;
+	u32 pad12[190];
+	u32 pl310_test_operation;
+	u32 pad13[3];
+	u32 pl310_line_data;
+	u32 pad14[7];
+	u32 pl310_line_tag;
+	u32 pad15[3];
+	u32 pl310_debug_ctrl;
+	u32 pad16[7];
+	u32 pl310_prefetch_ctrl;
+	u32 pad17[7];
+	u32 pl310_power_ctrl;
 };
 
 void pl310_inval_all(void);