diff options
| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2017-08-21 06:06:51 (GMT) |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-08-23 04:12:21 (GMT) |
| commit | 7071480a771853f1ddca05199da2d07e3fc0cb03 (patch) | |
| tree | 7dedd98278183da16d546bdf49e2f3f0ed1a3831 /arch/arm/include/asm | |
| parent | 429404572a29e2fac36749ed957cd76ce5eddc70 (diff) | |
| download | u-boot-7071480a771853f1ddca05199da2d07e3fc0cb03.tar.xz | |
armv8: fsl-layerscape: Support to add RGMII for ls1088aqds
This patch adds support RGMII protocol
NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index a2c7578..12fd6b8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -159,6 +159,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device); enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); int is_serdes_prtcl_valid(int serdes, u32 prtcl); int serdes_get_number(int serdes, int cfg); +void fsl_rgmii_init(void); #ifdef CONFIG_FSL_LSCH2 const char *serdes_clock_to_string(u32 clock); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 18e75dc..647bc9c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -260,6 +260,12 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 #elif defined(CONFIG_ARCH_LS1088A) +#define FSL_CHASSIS3_EC1_REGSR 26 +#define FSL_CHASSIS3_EC2_REGSR 26 +#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038 +#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF |