diff options
author | Tom Rini <trini@konsulko.com> | 2017-05-08 19:44:44 (GMT) |
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committer | Tom Rini <trini@konsulko.com> | 2017-05-08 19:44:44 (GMT) |
commit | a6d4cd4778bcc30f451f2d5d92ec4722ff5b71cc (patch) | |
tree | a20f104d8896941c598f2fcb61ce26c327959cd9 /arch/arm/include/asm | |
parent | ee3c6532be343e495d11adfe15a457d24d9747d9 (diff) | |
parent | 5a49b2929c0c73e43470cc53b80a6dfa47b5efda (diff) | |
download | u-boot-a6d4cd4778bcc30f451f2d5d92ec4722ff5b71cc.tar.xz |
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 18 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/display2.h | 124 |
3 files changed, 148 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index a44ea77..faa1479 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -25,7 +25,7 @@ struct sunxi_ccm_reg { u32 pll6_cfg; /* 0x28 pll6 control */ u32 reserved5; u32 pll7_cfg; /* 0x30 pll7 control */ - u32 reserved6; + u32 sata_pll_cfg; /* 0x34 SATA pll control (R40 only) */ u32 pll8_cfg; /* 0x38 pll8 control */ u32 reserved7; u32 mipi_pll_cfg; /* 0x40 MIPI pll control */ @@ -58,7 +58,8 @@ struct sunxi_ccm_reg { u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ u32 reserved10[2]; u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ - u32 reserved11[2]; + u32 reserved11; + u32 sata_clk_cfg; /* 0xc8 SATA clock control (R40 only) */ u32 usb_clk_cfg; /* 0xcc USB clock control */ u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */ u32 reserved12[7]; @@ -224,6 +225,8 @@ struct sunxi_ccm_reg { #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) #define CCM_PLL6_CTRL_LOCK (1 << 28) +#define CCM_SATA_PLL_DEFAULT 0x90005811 /* 100 MHz */ + #define CCM_MIPI_PLL_CTRL_M_SHIFT 0 #define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) #define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0) @@ -280,7 +283,12 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #endif +#ifndef CONFIG_MACH_SUN8I_R40 #define AHB_GATE_OFFSET_USB0 24 +#else +#define AHB_GATE_OFFSET_USB0 25 +#define AHB_GATE_OFFSET_SATA 24 +#endif #define AHB_GATE_OFFSET_MCTL 14 #define AHB_GATE_OFFSET_GMAC 17 #define AHB_GATE_OFFSET_NAND0 13 @@ -315,6 +323,9 @@ struct sunxi_ccm_reg { #define CCM_MMC_CTRL_PLL6 (0x1 << 24) #define CCM_MMC_CTRL_ENABLE (0x1 << 31) +#define CCM_SATA_CTRL_ENABLE (0x1 << 31) +#define CCM_SATA_CTRL_USE_EXTCLK (0x1 << 24) + #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) #define CCM_USB_CTRL_PHY2_RST (0x1 << 2) @@ -417,6 +428,9 @@ struct sunxi_ccm_reg { #define CCM_PLL11_PATTERN 0xf5860000 /* ahb_reset0 offsets */ +#ifdef CONFIG_MACH_SUN8I_R40 +#define AHB_RESET_OFFSET_SATA 24 +#endif #define AHB_RESET_OFFSET_GMAC 17 #define AHB_RESET_OFFSET_MCTL 14 #define AHB_RESET_OFFSET_MMC3 11 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 88c3f13..6aa5e91 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -18,6 +18,8 @@ #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ +#define SUNXI_DE2_BASE 0x01000000 + #ifdef CONFIG_MACH_SUN8I_A83T #define SUNXI_CPUCFG_BASE 0x01700000 #endif @@ -46,7 +48,9 @@ #define SUNXI_USB1_BASE 0x01c14000 #endif #define SUNXI_SS_BASE 0x01c15000 +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) #define SUNXI_HDMI_BASE 0x01c16000 +#endif #define SUNXI_SPI2_BASE 0x01c17000 #define SUNXI_SATA_BASE 0x01c18000 #ifdef CONFIG_SUNXI_GEN_SUN4I @@ -164,6 +168,10 @@ defined(CONFIG_MACH_SUN50I) #define SUNXI_MP_BASE 0x01e80000 #define SUNXI_AVG_BASE 0x01ea0000 +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) +#define SUNXI_HDMI_BASE 0x01ee0000 +#endif + #define SUNXI_RTC_BASE 0x01f00000 #define SUNXI_PRCM_BASE 0x01f01400 diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h new file mode 100644 index 0000000..b5875f9 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/display2.h @@ -0,0 +1,124 @@ +/* + * Sunxi platform display controller register and constant defines + * + * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> + * + * Based on out of tree Linux DRM driver defines: + * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr> + * Copyright (c) 2016 Allwinnertech Co., Ltd. +* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DISPLAY2_H +#define _SUNXI_DISPLAY2_H + +/* internal clock settings */ +struct de_clk { + u32 gate_cfg; + u32 bus_cfg; + u32 rst_cfg; + u32 div_cfg; + u32 sel_cfg; +}; + +/* global control */ +struct de_glb { + u32 ctl; + u32 status; + u32 dbuff; + u32 size; +}; + +/* alpha blending */ +struct de_bld { + u32 fcolor_ctl; + struct { + u32 fcolor; + u32 insize; + u32 offset; + u32 dum; + } attr[4]; + u32 dum0[15]; + u32 route; + u32 premultiply; + u32 bkcolor; + u32 output_size; + u32 bld_mode[4]; + u32 dum1[4]; + u32 ck_ctl; + u32 ck_cfg; + u32 dum2[2]; + u32 ck_max[4]; + u32 dum3[4]; + u32 ck_min[4]; + u32 dum4[3]; + u32 out_ctl; +}; + +/* VI channel */ +struct de_vi { + struct { + u32 attr; + u32 size; + u32 coord; + u32 pitch[3]; + u32 top_laddr[3]; + u32 bot_laddr[3]; + } cfg[4]; + u32 fcolor[4]; + u32 top_haddr[3]; + u32 bot_haddr[3]; + u32 ovl_size[2]; + u32 hori[2]; + u32 vert[2]; +}; + +struct de_ui { + struct { + u32 attr; + u32 size; + u32 coord; + u32 pitch; + u32 top_laddr; + u32 bot_laddr; + u32 fcolor; + u32 dum; + } cfg[4]; + u32 top_haddr; + u32 bot_haddr; + u32 ovl_size; +}; + +/* + * DE register constants. + */ +#define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000) +#define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000) + +#define SUNXI_DE2_MUX_GLB_REGS 0x00000 +#define SUNXI_DE2_MUX_BLD_REGS 0x01000 +#define SUNXI_DE2_MUX_CHAN_REGS 0x02000 +#define SUNXI_DE2_MUX_CHAN_SZ 0x1000 +#define SUNXI_DE2_MUX_VSU_REGS 0x20000 +#define SUNXI_DE2_MUX_GSU1_REGS 0x30000 +#define SUNXI_DE2_MUX_GSU2_REGS 0x40000 +#define SUNXI_DE2_MUX_GSU3_REGS 0x50000 +#define SUNXI_DE2_MUX_FCE_REGS 0xa0000 +#define SUNXI_DE2_MUX_BWS_REGS 0xa2000 +#define SUNXI_DE2_MUX_LTI_REGS 0xa4000 +#define SUNXI_DE2_MUX_PEAK_REGS 0xa6000 +#define SUNXI_DE2_MUX_ASE_REGS 0xa8000 +#define SUNXI_DE2_MUX_FCC_REGS 0xaa000 +#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000 + +#define SUNXI_DE2_FORMAT_XRGB_8888 4 +#define SUNXI_DE2_FORMAT_RGB_565 10 + +#define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0) +#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0) +#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8) + +#define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1)) + +#endif /* _SUNXI_DISPLAY2_H */ |