diff options
author | York Sun <york.sun@nxp.com> | 2016-04-04 18:41:26 (GMT) |
---|---|---|
committer | York Sun <york.sun@nxp.com> | 2016-04-06 17:26:46 (GMT) |
commit | 3c1d218a1d3048fb576677c47eab43049d0b7778 (patch) | |
tree | fac5c6482522cef5563f368ee2777f4ed274759e /arch/arm/include | |
parent | 2a5558399828e24fce9e948288a88cd28887875e (diff) | |
download | u-boot-3c1d218a1d3048fb576677c47eab43049d0b7778.tar.xz |
armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 9 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/fsl_secure_boot.h | 12 |
5 files changed, 12 insertions, 16 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ceefe43..10d17b2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -23,16 +23,11 @@ */ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#ifdef CONFIG_LS2080A -#define CONFIG_NUM_DDR_CONTROLLERS 2 -#endif -#ifdef CONFIG_LS2085A #define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_HAS_DP_DDR -#endif +#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 9054942..702b9fa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -206,7 +206,7 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index d1fbde7..f71c2c1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -9,7 +9,7 @@ #include <config.h> -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A enum srds_prtcl { NONE = 0, PCIE1, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 56989e1..831d817 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -94,4 +94,7 @@ void cpu_name(char *name); #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 void erratum_a009635(void); #endif + +bool soc_has_dp_ddr(void); +bool soc_has_aiop(void); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index d576f2e..53cd755 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -44,15 +44,14 @@ #endif -#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\ - defined(CONFIG_LS2085A) +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit - * Similiarly for LS2080 and LS2085 + * Similiarly for LS2080 */ #define CONFIG_ESBC_ADDR_64BIT #endif -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xa0000000;" \ "setenv initrd_high 0xcfffffff;" \ @@ -66,12 +65,11 @@ /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\ - defined(CONFIG_LS2085A) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif /* The address needs to be modified according to NOR and DDR memory map */ -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_BS_HDR_ADDR_FLASH 0x583920000 #define CONFIG_BS_ADDR_FLASH 0x583900000 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 |