diff options
author | Hans de Goede <hdegoede@redhat.com> | 2015-08-08 10:36:44 (GMT) |
---|---|---|
committer | Hans de Goede <hdegoede@redhat.com> | 2015-08-14 06:37:38 (GMT) |
commit | 49043cbad1db2e97daffe54d5ee32103c11dd4fd (patch) | |
tree | 8bcf19d4634c6ab93278d00323548486e02254c7 /arch/arm/include | |
parent | fbf10ae98657f1a888b670078f4eb18f9172c834 (diff) | |
download | u-boot-49043cbad1db2e97daffe54d5ee32103c11dd4fd.tar.xz |
sunxi: clock: Add clock_get_pll3() helper function
Add a helper function to get the pll3 clock rate.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index b397809..1a0b525 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -208,6 +208,8 @@ struct sunxi_ccm_reg { #define CCM_AHB_GATE_DLL (0x1 << 15) #define CCM_AHB_GATE_ACE (0x1 << 16) +#define CCM_PLL3_CTRL_M_SHIFT 0 +#define CCM_PLL3_CTRL_M_MASK (0x7f << CCM_PLL3_CTRL_M_SHIFT) #define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0) #define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15) #define CCM_PLL3_CTRL_EN (0x1 << 31) @@ -347,6 +349,7 @@ struct sunxi_ccm_reg { #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int hz); void clock_set_pll3(unsigned int hz); +unsigned int clock_get_pll3(void); unsigned int clock_get_pll5p(void); unsigned int clock_get_pll6(void); #endif diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 06c6feb..a197345 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -179,7 +179,11 @@ struct sunxi_ccm_reg { #define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) #define CCM_PLL1_CTRL_EN (0x1 << 31) +#define CCM_PLL3_CTRL_M_SHIFT 0 +#define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT) #define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0) +#define CCM_PLL3_CTRL_N_SHIFT 8 +#define CCM_PLL3_CTRL_N_MASK (0x7f << CCM_PLL3_CTRL_N_SHIFT) #define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) #define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24) #define CCM_PLL3_CTRL_EN (0x1 << 31) @@ -360,6 +364,7 @@ void clock_set_pll1(unsigned int hz); void clock_set_pll3(unsigned int hz); void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); void clock_set_pll11(unsigned int clk, bool sigma_delta_enable); +unsigned int clock_get_pll3(void); unsigned int clock_get_pll6(void); #endif |