diff options
| author | Thomas Abraham <thomas.ab@samsung.com> | 2015-08-03 12:28:01 (GMT) |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-08-17 04:06:55 (GMT) |
| commit | 14a66afead568a5c3a6bb49782432bea3b397fb8 (patch) | |
| tree | fc1d02ac85610879c1ddd5f464c2ff82c90e796a /arch/arm/mach-exynos | |
| parent | 77b55e8cfcee9ce1a973bf4dad3e160dd0be01f3 (diff) | |
| download | u-boot-14a66afead568a5c3a6bb49782432bea3b397fb8.tar.xz | |
ARM: exynos: fix regression for Origen4210
The do_lowlevel_init() function includes certian CA15 specific L2 cache
configuration which is only applicable on Exynos5420 and members of its
family. Fix the regression on Origen4210 by skipping the Exynos5420
specific portions of the code.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos')
| -rw-r--r-- | arch/arm/mach-exynos/common_setup.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/lowlevel_init.c | 4 |
2 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h index 5235abb..67aac2d 100644 --- a/arch/arm/mach-exynos/common_setup.h +++ b/arch/arm/mach-exynos/common_setup.h @@ -60,7 +60,7 @@ enum l2_cache_params { }; -#ifndef CONFIG_SYS_L2CACHE_OFF +#if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420) /* * Configure L2CTLR to get timings that keep us from hanging/crashing. * diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 3774607..6c39cb2 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -175,7 +175,7 @@ int do_lowlevel_init(void) arch_cpu_init(); -#ifndef CONFIG_SYS_L2CACHE_OFF +#if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420) /* * Init L2 cache parameters here for use by boot and resume * @@ -188,9 +188,7 @@ int do_lowlevel_init(void) configure_l2_actlr(); dsb(); isb(); -#endif -#ifdef CONFIG_EXYNOS5420 relocate_wait_code(); /* Reconfigure secondary cores */ |