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authorLokesh Vutla <lokeshvutla@ti.com>2015-07-28 08:46:45 (GMT)
committerTom Rini <trini@konsulko.com>2015-08-13 00:47:53 (GMT)
commit74af583e9f7a255443d8f625c8dce6da7b9703be (patch)
treefbd63bb5fad0a796a8dcfcf4cfca0623fa235f17 /arch/arm/mach-keystone/include/mach/hardware.h
parent7b50e1599f4e6551a3348ca5f061a596f6f6896e (diff)
downloadu-boot-74af583e9f7a255443d8f625c8dce6da7b9703be.tar.xz
ARM: keystone2: Use common structure for PLLs
Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-keystone/include/mach/hardware.h')
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index cf32ae5..53f28ec 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -165,6 +165,8 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)