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| author | Tom Rini <trini@konsulko.com> | 2015-03-10 23:09:18 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-03-10 23:09:18 (GMT) |
| commit | b79dadf846e5e140e261bbfa4decd024357702d7 (patch) | |
| tree | bbfed4207c806f34ceb4b608e62cc4fbfa98f91f /arch/arm/mach-orion5x/lowlevel_init.S | |
| parent | 1fc42018a0fe833a4332f8f32d6aeb675f3dcd1d (diff) | |
| parent | d5338c693e6a35a7108c184839d688a7377d117c (diff) | |
| download | u-boot-b79dadf846e5e140e261bbfa4decd024357702d7.tar.xz | |
Merge branch 'master' of git://git.denx.de/u-boot-tegra
Conflicts:
README
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-orion5x/lowlevel_init.S')
| -rw-r--r-- | arch/arm/mach-orion5x/lowlevel_init.S | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index 4dacc29..51a8b3c 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -62,14 +62,16 @@ /* * Low-level init happens right after start.S has switched to SVC32, * flushed and disabled caches and disabled MMU. We're still running - * from the boot chip select, so the first thing we should do is set - * up RAM for us to relocate into. + * from the boot chip select, so the first thing SPL should do is to + * set up the RAM to copy U-Boot into. */ .globl lowlevel_init lowlevel_init: +#ifdef CONFIG_SPL_BUILD + /* Use 'r4 as the base for internal register accesses */ ldr r4, =ORION5X_REGS_PHY_BASE @@ -273,5 +275,13 @@ lowlevel_init: orr r2, r2, r6 str r2, [r3, #0x484] + /* enable for 2 GB DDR; detection should find out real amount */ + sub r6, r6, r6 + str r6, [r3, #0x500] + ldr r6, =0x7fff0001 + str r6, [r3, #0x504] + +#endif /* CONFIG_SPL_BUILD */ + /* Return to U-boot via saved link register */ mov pc, lr |