diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2017-04-25 18:44:39 (GMT) |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2017-05-18 09:33:17 (GMT) |
| commit | 177ba1f9273f96402a01a34e70d78b3b14b12625 (patch) | |
| tree | 1d03d9ac1d207d5d8934e20aaf0e02fded67cd8d /arch/arm/mach-socfpga/clock_manager.c | |
| parent | 827e6a7e0dc0c457a51cdd8b1b81d4e895289046 (diff) | |
| download | u-boot-177ba1f9273f96402a01a34e70d78b3b14b12625.tar.xz | |
arm: socfpga: Add clock driver for Arria 10
Add clock driver support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/clock_manager.c')
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 8051995..cb6ae03 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -19,7 +19,12 @@ void cm_wait_for_lock(u32 mask) u32 inter_val; u32 retry = 0; do { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) inter_val = readl(&clock_manager_base->inter) & mask; +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + inter_val = readl(&clock_manager_base->stat) & mask; +#endif + /* Wait for stable lock */ if (inter_val == mask) retry++; else @@ -44,7 +49,12 @@ int set_cpu_clk_info(void) gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; gd->bd->bi_dsp_freq = 0; + +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + gd->bd->bi_ddr_freq = 0; +#endif return 0; } |