arm: socfpga: clock: Clean up pll_config.h

Extract the clock configuration horribleness caused by pll_config.h in
the following manner.

First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.

The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.

The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.

Signed-off-by: Marek Vasut <marex@denx.de>

1 files changed, 14 insertions, 14 deletions

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 74aa1d9..1341df4 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -88,7 +88,7 @@ static void cm_write_with_phase(uint32_t value,
  * Ungate clocks
  */
 
-void cm_basic_init(const struct cm_config *cfg)
+void cm_basic_init(const struct cm_config * const cfg)
 {
 	uint32_t start, timeout;
 
@@ -336,7 +336,7 @@ static unsigned int cm_get_main_vco_clk_hz(void)
 
 	/* get the main VCO clock */
 	reg = readl(&clock_manager_base->main_pll.vco);
-	clock = CONFIG_HPS_CLK_OSC1_HZ;
+	clock = cm_get_osc_clk_hz(1);
 	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
 		  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
 	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
@@ -354,11 +354,11 @@ static unsigned int cm_get_per_vco_clk_hz(void)
 	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
 	      CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
-		clock = CONFIG_HPS_CLK_OSC1_HZ;
+		clock = cm_get_osc_clk_hz(1);
 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-		clock = CONFIG_HPS_CLK_OSC2_HZ;
+		clock = cm_get_osc_clk_hz(2);
 	else if (reg == CLKMGR_VCO_SSRC_F2S)
-		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		clock = cm_get_f2s_per_ref_clk_hz();
 
 	/* get the PER VCO clock */
 	reg = readl(&clock_manager_base->per_pll.vco);
@@ -393,11 +393,11 @@ unsigned long cm_get_sdram_clk_hz(void)
 	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
 	      CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
-		clock = CONFIG_HPS_CLK_OSC1_HZ;
+		clock = cm_get_osc_clk_hz(1);
 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-		clock = CONFIG_HPS_CLK_OSC2_HZ;
+		clock = cm_get_osc_clk_hz(2);
 	else if (reg == CLKMGR_VCO_SSRC_F2S)
-		clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+		clock = cm_get_f2s_sdr_ref_clk_hz();
 
 	/* get the SDRAM VCO clock */
 	reg = readl(&clock_manager_base->sdr_pll.vco);
@@ -459,7 +459,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
 	      CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
 
 	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
-		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		clock = cm_get_f2s_per_ref_clk_hz();
 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
 		clock = cm_get_main_vco_clk_hz();
 
@@ -489,7 +489,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
 	      CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
 
 	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
-		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		clock = cm_get_f2s_per_ref_clk_hz();
 	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
 		clock = cm_get_main_vco_clk_hz();
 
@@ -524,10 +524,10 @@ static void cm_print_clock_quick_summary(void)
 {
 	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
 	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
-	printf("EOSC1       %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
-	printf("EOSC2       %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
-	printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
-	printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
+	printf("EOSC1       %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
+	printf("EOSC2       %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
+	printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
+	printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
 	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
 	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
 	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);